From 8bc9732d49fe645f29bc840c503ddb94a07f6e4c Mon Sep 17 00:00:00 2001 From: gatecat Date: Fri, 14 May 2021 22:44:06 +0100 Subject: [PATCH] mistral: PKREG bits appear to be mirrored within a half? Signed-off-by: gatecat --- mistral/bitstream.cc | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/mistral/bitstream.cc b/mistral/bitstream.cc index 6921bbb5..8e78b228 100644 --- a/mistral/bitstream.cc +++ b/mistral/bitstream.cc @@ -246,8 +246,9 @@ struct MistralBitgen cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true); // Flipflop configuration const std::array ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL}; - const std::array pkreg{CycloneV::TPKREG0, CycloneV::TPKREG1, CycloneV::BPKREG0, - CycloneV::BPKREG1}; + // This isn't a typo; the *PKREG* bits really are mirrored. + const std::array pkreg{CycloneV::TPKREG1, CycloneV::TPKREG0, CycloneV::BPKREG1, + CycloneV::BPKREG0}; const std::array clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL}, clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS},