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mistral: PKREG bits appear to be mirrored within a half?

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-14 22:44:06 +01:00
parent 757a10c247
commit 8bc9732d49
1 changed files with 3 additions and 2 deletions
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5
mistral/bitstream.cc
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@ -246,8 +246,9 @@ struct MistralBitgen
cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true); cv->bmux_b_set(CycloneV::LAB, pos, CycloneV::BTO_DIS, alm, true);
// Flipflop configuration // Flipflop configuration
const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL}; const std::array<CycloneV::bmux_type_t, 2> ef_sel{CycloneV::TEF_SEL, CycloneV::BEF_SEL};
const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG0, CycloneV::TPKREG1, CycloneV::BPKREG0, // This isn't a typo; the *PKREG* bits really are mirrored.
CycloneV::BPKREG1}; const std::array<CycloneV::bmux_type_t, 4> pkreg{CycloneV::TPKREG1, CycloneV::TPKREG0, CycloneV::BPKREG1,
CycloneV::BPKREG0};
const std::array<CycloneV::bmux_type_t, 2> clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL}, const std::array<CycloneV::bmux_type_t, 2> clk_sel{CycloneV::TCLK_SEL, CycloneV::BCLK_SEL},
clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS}, clr_sel{CycloneV::TCLR_SEL, CycloneV::BCLR_SEL}, sclr_dis{CycloneV::TSCLR_DIS, CycloneV::BSCLR_DIS},