From 8c19e6f83a7835713f21c8b5ff68869e9b8a9e32 Mon Sep 17 00:00:00 2001 From: Miodrag Milanovic Date: Thu, 20 Apr 2023 13:17:40 +0200 Subject: [PATCH] clangformat --- gui/generic/mainwindow.cc | 8 +++-- machxo2/arch.cc | 3 +- machxo2/arch.h | 13 ++++---- machxo2/arch_place.cc | 3 +- machxo2/baseconfigs.cc | 3 +- machxo2/bitstream.cc | 66 +++++++++++++++++++-------------------- machxo2/cells.h | 2 -- machxo2/pack.cc | 9 ++---- 8 files changed, 52 insertions(+), 55 deletions(-) diff --git a/gui/generic/mainwindow.cc b/gui/generic/mainwindow.cc index aeb5c04b..54fe6f3e 100644 --- a/gui/generic/mainwindow.cc +++ b/gui/generic/mainwindow.cc @@ -42,9 +42,11 @@ void MainWindow::newContext(Context *ctx) void MainWindow::createMenu() {} -void MainWindow::new_proj() { - QMessageBox::critical(0, "Error", "Creating a new project not supported in Viaduct mode, please re-start from command line."); - std::exit(1); +void MainWindow::new_proj() +{ + QMessageBox::critical(0, "Error", + "Creating a new project not supported in Viaduct mode, please re-start from command line."); + std::exit(1); } NEXTPNR_NAMESPACE_END diff --git a/machxo2/arch.cc b/machxo2/arch.cc index 6092d9bd..6aadd2d1 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -631,7 +631,8 @@ std::vector> Arch::getWireAttrs(WireId wire) co bool Arch::is_spine_row(int row) const { for (auto &spine : chip_info->spines) { - if (row==spine.row) return true; + if (row == spine.row) + return true; } return false; } diff --git a/machxo2/arch.h b/machxo2/arch.h index fbb1d3b5..222390e8 100644 --- a/machxo2/arch.h +++ b/machxo2/arch.h @@ -875,11 +875,11 @@ struct Arch : BaseArch int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pip_data[pip.index].pip_type; } BelId get_package_pin_bel(const std::string &pin) const; - //std::string get_bel_package_pin(BelId bel) const; - //int get_pio_bel_bank(BelId bel) const; - // For getting GCLK, PLL, Vref, etc, pins - //std::string get_pio_function_name(BelId bel) const; - //BelId get_pio_by_function_name(const std::string &name) const; + // std::string get_bel_package_pin(BelId bel) const; + // int get_pio_bel_bank(BelId bel) const; + // For getting GCLK, PLL, Vref, etc, pins + // std::string get_pio_function_name(BelId bel) const; + // BelId get_pio_by_function_name(const std::string &name) const; PortType getBelPinType(BelId bel, IdString pin) const override; @@ -903,7 +903,7 @@ struct Arch : BaseArch float getDelayNS(delay_t v) const override { return v; } delay_t getDelayFromNS(float ns) const override { return ns; } uint32_t getDelayChecksum(delay_t v) const override { return v; } - //bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override; + // bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override; // ------------------------------------------------- @@ -975,7 +975,6 @@ struct Arch : BaseArch mutable std::vector tile_status; // ------------------------------------------------- - }; NEXTPNR_NAMESPACE_END diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc index 6307fdb6..97f7226f 100644 --- a/machxo2/arch_place.cc +++ b/machxo2/arch_place.cc @@ -149,7 +149,8 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const if (ff != nullptr) { if (found_global_dpram) { // Do not allow SLICEC to have FF if there is already RAMW in it - if (i==4 || i==5) return false; + if (i == 4 || i == 5) + return false; CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv); CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv); } diff --git a/machxo2/baseconfigs.cc b/machxo2/baseconfigs.cc index 29c12c72..7346ed82 100644 --- a/machxo2/baseconfigs.cc +++ b/machxo2/baseconfigs.cc @@ -148,7 +148,6 @@ void config_empty_lcmxo3_2100(ChipConfig &cc) cc.tiles["PT4:CFG0"].add_unknown(5, 32); cc.tiles["PT4:CFG0"].add_unknown(5, 36); - cc.tiles["PT7:CFG3"].add_unknown(5, 18); } @@ -227,7 +226,7 @@ void config_empty_lcmxo3_9400(ChipConfig &cc) cc.tiles["EBR_R15C42:EBR1_10K"].add_unknown(0, 12); cc.tiles["EBR_R15C45:EBR1_10K"].add_unknown(0, 12); cc.tiles["EBR_R15C48:EBR1_10K"].add_unknown(0, 12); - + cc.tiles["EBR_R8C2:EBR1"].add_unknown(0, 12); cc.tiles["EBR_R8C5:EBR1"].add_unknown(0, 12); cc.tiles["EBR_R8C8:EBR1"].add_unknown(0, 12); diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index cbd3bdea..98af4866 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -108,13 +108,13 @@ struct MachXO2Bitgen std::string pio_name = "W1_" + basename; if (ctx->verbose) log_info("PIO wire %s was adjusted by W1 to form Trellis name %s.\n", ctx->nameOfWire(wire), - pio_name.c_str()); + pio_name.c_str()); return pio_name; } else if (wire.location.x == max_col) { std::string pio_name = "E1_" + basename; if (ctx->verbose) log_info("PIO wire %s was adjusted by E1 to form Trellis name %s.\n", ctx->nameOfWire(wire), - pio_name.c_str()); + pio_name.c_str()); return pio_name; } } @@ -206,16 +206,13 @@ struct MachXO2Bitgen { static const std::set pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"}; static const std::set pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"}; - static const std::set pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0", - "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5", - "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5", - "PIC_L2_VREF4", "PIC_L2_VREF5", - "PIC_L3_VREF4", "PIC_L3_VREF5", - "LLC0PIC", "LLC1PIC", - "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"}; - static const std::set pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0", - "PIC_R0_256", "PIC_R1_640", "PIC_RS0_256", - "LRC1PIC1", "LRC1PIC2", "URC1PIC"}; + static const std::set pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", + "PIC_LS0", "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5", + "PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5", "PIC_L2_VREF4", + "PIC_L2_VREF5", "PIC_L3_VREF4", "PIC_L3_VREF5", "LLC0PIC", + "LLC1PIC", "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"}; + static const std::set pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0", "PIC_R0_256", "PIC_R1_640", + "PIC_RS0_256", "LRC1PIC1", "LRC1PIC2", "URC1PIC"}; std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { @@ -241,14 +238,17 @@ struct MachXO2Bitgen static const std::set ebr1 = {"EBR1", "EBR1_10K"}; static const std::set ebr2 = {"EBR2", "EBR2_END", "EBR2_10K", "EBR2_END_10K"}; tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0)); - tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, ebr1)); - tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, ebr2)); - static const std::set cib_ebr0 = {"CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3", "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"}; + tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, ebr1)); + tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, ebr2)); + static const std::set cib_ebr0 = { + "CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3", + "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"}; static const std::set cib_ebr1 = {"CIB_EBR1", "CIB_EBR1_10K"}; - static const std::set cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0", "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"}; + static const std::set cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0", + "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"}; tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, cib_ebr0)); - tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, cib_ebr1)); - tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, cib_ebr2)); + tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, cib_ebr1)); + tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, cib_ebr2)); return tiles; } @@ -260,9 +260,9 @@ struct MachXO2Bitgen Loc loc = ctx->getBelLocation(bel); if (name == "LPLL") { - tiles.push_back(ctx->get_tile_by_type_loc(loc.y-1, loc.x-1, "GPLL_L0")); - } else if (name == "RPLL") { - tiles.push_back(ctx->get_tile_by_type_loc(loc.y+1, loc.x-1, "GPLL_R0")); + tiles.push_back(ctx->get_tile_by_type_loc(loc.y - 1, loc.x - 1, "GPLL_L0")); + } else if (name == "RPLL") { + tiles.push_back(ctx->get_tile_by_type_loc(loc.y + 1, loc.x - 1, "GPLL_R0")); } else { NPNR_ASSERT_FALSE_STR("bad PLL loc " + name); } @@ -272,7 +272,8 @@ struct MachXO2Bitgen void set_pip(ChipConfig &cc, PipId pip) { std::string tile = ctx->get_pip_tilename(pip); - std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get(); + std::string tile_type = + ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get(); std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); @@ -365,7 +366,7 @@ struct MachXO2Bitgen int lut_init = int_or_default(ci->params, id_INITVAL); cc.tiles[tname].add_enum(slice + ".MODE", mode); cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT", - int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16)); + int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16)); if (mode == "CCU2") { cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES")); } else { @@ -460,7 +461,7 @@ struct MachXO2Bitgen tg.config.add_word(ebr + ".WID", int_to_bitvector(int_or_default(ci->attrs, id_WID, 0), 9)); - // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals + // Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) { for (int bit = 0; bit < 3; bit++) { std::string sig = port.first + std::to_string(bit); @@ -476,7 +477,6 @@ struct MachXO2Bitgen if (!ci->ramInfo.is_pdp) { tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA")); tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB")); - } tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA")); tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB")); @@ -695,8 +695,8 @@ struct MachXO2Bitgen } else if (ci->type == id_EHXPLLJ) { write_pll(ci); } else if (ci->type == id_GSR) { - cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum( - "GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW")); + cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.GSRMODE", + str_or_default(ci->params, id_MODE, "ACTIVE_LOW")); cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.SYNCMODE", str_or_default(ci->params, id_SYNCMODE, "ASYNC")); } else if (ci->type == id_JTAGF) { @@ -705,17 +705,17 @@ struct MachXO2Bitgen cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("JTAG.ER2", str_or_default(ci->params, id_ER2, "ENABLED")); } else if (ci->type == id_TSALL) { - cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum( - "TSALL.MODE", str_or_default(ci->params, id_MODE, "TSALL")); - cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum( - "TSALL.TSALL", str_or_default(ci->params, id_TSALL, "TSALL")); + cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.MODE", + str_or_default(ci->params, id_MODE, "TSALL")); + cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.TSALL", + str_or_default(ci->params, id_TSALL, "TSALL")); } else if (ci->type == id_START) { cc.tiles[ctx->get_tile_by_type("CIB_CFG0")].add_enum( - "START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK")); + "START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK")); } else if (ci->type == id_CLKDIVC) { Loc loc = ctx->getBelLocation(ci->bel); bool t = loc.y < 2; - std::string clkdiv = (t ? "T": "B") + std::string("CLKDIV") + std::to_string(loc.z); + std::string clkdiv = (t ? "T" : "B") + std::string("CLKDIV") + std::to_string(loc.z); std::string tile = ctx->get_tile_by_type(t ? "PIC_T_DUMMY_VIQ" : "PIC_B_DUMMY_VIQ_VREF"); cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0")); cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED")); diff --git a/machxo2/cells.h b/machxo2/cells.h index dd59e073..498fabaa 100644 --- a/machxo2/cells.h +++ b/machxo2/cells.h @@ -54,8 +54,6 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector> &created_cells, pool &todelete_cells); - - NEXTPNR_NAMESPACE_END #endif diff --git a/machxo2/pack.cc b/machxo2/pack.cc index 74d15056..f6f7027e 100644 --- a/machxo2/pack.cc +++ b/machxo2/pack.cc @@ -274,10 +274,7 @@ class MachXO2Packer } // Return true if an port is a top level port that provides its own IOBUF - bool is_top_port(PortRef &port) - { - return false; - } + bool is_top_port(PortRef &port) { return false; } // Return true if a net only drives a top port bool drives_top_port(NetInfo *net, PortRef &tp) @@ -788,14 +785,14 @@ class MachXO2Packer std::unique_ptr ram_comb[4]; for (int i = 0; i < 4; i++) { ram_comb[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB, - ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i)); + ci->name.str(ctx) + "$DPRAM_COMB" + std::to_string(i)); dram_to_comb(ctx, ci, ram_comb[i].get(), ramw_slice.get(), i); } // Create 'block' SLICEs as a placement hint that these cells are mutually exclusive with the RAMW std::unique_ptr ramw_block[2]; for (int i = 0; i < 2; i++) { ramw_block[i] = create_machxo2_cell(ctx, id_TRELLIS_COMB, - ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i)); + ci->name.str(ctx) + "$RAMW_BLOCK" + std::to_string(i)); ramw_block[i]->params[id_MODE] = std::string("RAMW_BLOCK"); }