caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

clangformat

Browse Source
This commit is contained in:
Miodrag Milanovic 2023-04-20 13:17:40 +02:00 committed by myrtle
parent 7ac3d0d901
commit 8c19e6f83a
8 changed files with 52 additions and 55 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
gui/generic/mainwindow.cc
View File

@ -42,8 +42,10 @@ void MainWindow::newContext(Context *ctx)
void MainWindow::createMenu() {}
void MainWindow::new_proj() {
QMessageBox::critical(0, "Error", "Creating a new project not supported in Viaduct mode, please re-start from command line.");
void MainWindow::new_proj()
{
QMessageBox::critical(0, "Error",
"Creating a new project not supported in Viaduct mode, please re-start from command line.");
std::exit(1);
}

3
machxo2/arch.cc
View File

@ -631,7 +631,8 @@ std::vector<std::pair<IdString, std::string>> Arch::getWireAttrs(WireId wire) co
bool Arch::is_spine_row(int row) const
{
for (auto &spine : chip_info->spines) {
if (row==spine.row) return true;
if (row == spine.row)
return true;
}
return false;
}

1
machxo2/arch.h
View File

@ -975,7 +975,6 @@ struct Arch : BaseArch<ArchRanges>
mutable std::vector<TileStatus> tile_status;
// -------------------------------------------------
};
NEXTPNR_NAMESPACE_END

3
machxo2/arch_place.cc
View File

@ -149,7 +149,8 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
if (ff != nullptr) {
if (found_global_dpram) {
// Do not allow SLICEC to have FF if there is already RAMW in it
if (i==4 || i==5) return false;
if (i == 4 || i == 5)
return false;
CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
}

1
machxo2/baseconfigs.cc
View File

@ -148,7 +148,6 @@ void config_empty_lcmxo3_2100(ChipConfig &cc)
cc.tiles["PT4:CFG0"].add_unknown(5, 32);
cc.tiles["PT4:CFG0"].add_unknown(5, 36);
cc.tiles["PT7:CFG3"].add_unknown(5, 18);
}

40
machxo2/bitstream.cc
View File

@ -206,16 +206,13 @@ struct MachXO2Bitgen
{
static const std::set<std::string> pio_t = {"PIC_T0", "PIC_T0_256", "PIC_TS0"};
static const std::set<std::string> pio_b = {"PIC_B0", "PIC_B0_256", "PIC_BS0_256"};
static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3", "PIC_LS0",
"PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
"PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5",
"PIC_L2_VREF4", "PIC_L2_VREF5",
"PIC_L3_VREF4", "PIC_L3_VREF5",
"LLC0PIC", "LLC1PIC",
"LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"};
static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0",
"PIC_R0_256", "PIC_R1_640", "PIC_RS0_256",
"LRC1PIC1", "LRC1PIC2", "URC1PIC"};
static const std::set<std::string> pio_l = {"PIC_L0", "PIC_L1", "PIC_L2", "PIC_L3",
"PIC_LS0", "PIC_L0_VREF3", "PIC_L0_VREF4", "PIC_L0_VREF5",
"PIC_L1_VREF3", "PIC_L1_VREF4", "PIC_L1_VREF5", "PIC_L2_VREF4",
"PIC_L2_VREF5", "PIC_L3_VREF4", "PIC_L3_VREF5", "LLC0PIC",
"LLC1PIC", "LLC0PIC_VREF3", "LLC3PIC_VREF3", "ULC3PIC"};
static const std::set<std::string> pio_r = {"PIC_R0", "PIC_R1", "PIC_RS0", "PIC_R0_256", "PIC_R1_640",
"PIC_RS0_256", "LRC1PIC1", "LRC1PIC2", "URC1PIC"};
std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get();
if (bel.location.y == 0) {
@ -243,9 +240,12 @@ struct MachXO2Bitgen
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, ebr1));
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, ebr2));
static const std::set<std::string> cib_ebr0 = {"CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3", "CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"};
static const std::set<std::string> cib_ebr0 = {
"CIB_EBR0", "CIB_EBR0_10K", "CIB_EBR0_END0", "CIB_EBR0_END0_10K", "CIB_EBR0_END0_DLL3",
"CIB_EBR0_END0_DLL5", "CIB_EBR0_END1", "CIB_EBR0_END2_DLL3", "CIB_EBR0_END2_DLL45"};
static const std::set<std::string> cib_ebr1 = {"CIB_EBR1", "CIB_EBR1_10K"};
static const std::set<std::string> cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0", "CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"};
static const std::set<std::string> cib_ebr2 = {"CIB_EBR2", "CIB_EBR2_10K", "CIB_EBR2_END0",
"CIB_EBR2_END1", "CIB_EBR2_END1_10K", "CIB_EBR2_END1_SP"};
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, cib_ebr0));
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 1, cib_ebr1));
tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x + 2, cib_ebr2));
@ -272,7 +272,8 @@ struct MachXO2Bitgen
void set_pip(ChipConfig &cc, PipId pip)
{
std::string tile = ctx->get_pip_tilename(pip);
std::string tile_type = ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
std::string tile_type =
ctx->chip_info->tiletype_names[ctx->tile_info(pip)->pip_data[pip.index].tile_type].get();
std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip));
cc.tiles[tile].add_arc(sink, source);
@ -476,7 +477,6 @@ struct MachXO2Bitgen
if (!ci->ramInfo.is_pdp) {
tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
}
tg.config.add_enum(ebr + ".CEAMUX", str_or_default(ci->params, id_CEAMUX, "CEA"));
tg.config.add_enum(ebr + ".CEBMUX", str_or_default(ci->params, id_CEBMUX, "CEB"));
@ -695,8 +695,8 @@ struct MachXO2Bitgen
} else if (ci->type == id_EHXPLLJ) {
write_pll(ci);
} else if (ci->type == id_GSR) {
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
"GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.GSRMODE",
str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("GSR.SYNCMODE",
str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
} else if (ci->type == id_JTAGF) {
@ -705,10 +705,10 @@ struct MachXO2Bitgen
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("JTAG.ER2",
str_or_default(ci->params, id_ER2, "ENABLED"));
} else if (ci->type == id_TSALL) {
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
"TSALL.MODE", str_or_default(ci->params, id_MODE, "TSALL"));
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum(
"TSALL.TSALL", str_or_default(ci->params, id_TSALL, "TSALL"));
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.MODE",
str_or_default(ci->params, id_MODE, "TSALL"));
cc.tiles[ctx->get_tile_by_type("CFG0")].add_enum("TSALL.TSALL",
str_or_default(ci->params, id_TSALL, "TSALL"));
} else if (ci->type == id_START) {
cc.tiles[ctx->get_tile_by_type("CIB_CFG0")].add_enum(
"START.STARTCLK", str_or_default(ci->params, id_STARTCLK, "STARTCLK"));

2
machxo2/cells.h
View File

@ -54,8 +54,6 @@ void dram_to_comb(Context *ctx, CellInfo *ram, CellInfo *comb, CellInfo *ramw, i
void nxio_to_tr(Context *ctx, CellInfo *nxio, CellInfo *trio, std::vector<std::unique_ptr<CellInfo>> &created_cells,
pool<IdString> &todelete_cells);
NEXTPNR_NAMESPACE_END
#endif

5
machxo2/pack.cc
View File

@ -274,10 +274,7 @@ class MachXO2Packer
}
// Return true if an port is a top level port that provides its own IOBUF
bool is_top_port(PortRef &port)
{
return false;
}
bool is_top_port(PortRef &port) { return false; }
// Return true if a net only drives a top port
bool drives_top_port(NetInfo *net, PortRef &tp)