Working BRAM
This commit is contained in:
Miodrag Milanovic
myrtle
parent
3a7770dca2
commit
8c38e7ba61
@ -154,6 +154,53 @@ struct MachXO2Bitgen
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return bv;
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return bv;
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}
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}
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inline int chtohex(char c)
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{
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static const std::string hex = "0123456789ABCDEF";
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return hex.find(std::toupper(c));
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}
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std::vector<bool> parse_init_str(const Property &p, int length, const char *cellname)
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{
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// Parse a string that may be binary or hex
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std::vector<bool> result;
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result.resize(length, false);
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if (p.is_string) {
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std::string str = p.as_string();
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NPNR_ASSERT(str.substr(0, 2) == "0x");
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// Lattice style hex string
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if (int(str.length()) > (2 + ((length + 3) / 4)))
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log_error("hex string value too long, expected up to %d chars and found %d.\n",
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(2 + ((length + 3) / 4)), int(str.length()));
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for (int i = 0; i < int(str.length()) - 2; i++) {
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char c = str.at((str.size() - i) - 1);
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int nibble = chtohex(c);
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if (nibble == (int)std::string::npos)
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log_error("hex string has invalid char '%c' at position %d.\n", c, i);
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result.at(i * 4) = nibble & 0x1;
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if (i * 4 + 1 < length)
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result.at(i * 4 + 1) = nibble & 0x2;
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if (i * 4 + 2 < length)
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result.at(i * 4 + 2) = nibble & 0x4;
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if (i * 4 + 3 < length)
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result.at(i * 4 + 3) = nibble & 0x8;
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}
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} else {
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result = p.as_bits();
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result.resize(length, false);
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}
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return result;
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}
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inline uint16_t bit_reverse(uint16_t x, int size)
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{
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uint16_t y = 0;
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for (int i = 0; i < size; i++)
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if (x & (1 << i))
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y |= (1 << ((size - 1) - i));
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return y;
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}
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// Get the PIC tile corresponding to a PIO bel
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// Get the PIC tile corresponding to a PIO bel
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std::string get_pic_tile(BelId bel)
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std::string get_pic_tile(BelId bel)
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{
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{
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@ -184,6 +231,21 @@ struct MachXO2Bitgen
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}
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}
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}
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}
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// Get the list of tiles corresponding to a blockram
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std::vector<std::string> get_bram_tiles(BelId bel)
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{
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std::vector<std::string> tiles;
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Loc loc = ctx->getBelLocation(bel);
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static const std::set<std::string> ebr0 = {"EBR0", "EBR0_END", "EBR0_10K", "EBR0_END_10K"};
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static const std::set<std::string> ebr1 = {"EBR1", "EBR1_10K"};
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static const std::set<std::string> ebr2 = {"EBR2", "EBR2_END", "EBR2_10K", "EBR2_END_10K"};
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tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x, ebr0));
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tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+1, ebr1));
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tiles.push_back(ctx->get_tile_by_type_loc(loc.y, loc.x+2, ebr2));
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return tiles;
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}
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// Get the list of tiles corresponding to a PLL
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// Get the list of tiles corresponding to a PLL
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std::vector<std::string> get_pll_tiles(BelId bel)
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std::vector<std::string> get_pll_tiles(BelId bel)
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{
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{
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@ -363,6 +425,78 @@ struct MachXO2Bitgen
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}
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}
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}
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}
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void write_bram(CellInfo *ci)
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{
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TileGroup tg;
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tg.tiles = get_bram_tiles(ci->bel);
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std::string ebr = "EBR";
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if (ci->ramInfo.is_pdp) {
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tg.config.add_enum(ebr + ".MODE", "PDPW8KC");
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tg.config.add_enum(ebr + ".PDPW8KC.DATA_WIDTH_R", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
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tg.config.add_enum(ebr + ".FIFO8KB.DATA_WIDTH_W", "18"); // default for PDPW8KC
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} else {
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tg.config.add_enum(ebr + ".MODE", "DP8KC");
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tg.config.add_enum(ebr + ".DP8KC.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
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tg.config.add_enum(ebr + ".DP8KC.DATA_WIDTH_B", intstr_or_default(ci->params, id_DATA_WIDTH_B, "18"));
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tg.config.add_enum(ebr + ".DP8KC.WRITEMODE_A", str_or_default(ci->params, id_WRITEMODE_A, "NORMAL"));
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tg.config.add_enum(ebr + ".DP8KC.WRITEMODE_B", str_or_default(ci->params, id_WRITEMODE_B, "NORMAL"));
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}
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auto csd_a = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_A, "0b000"), 3),
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csd_b = str_to_bitvector(str_or_default(ci->params, id_CSDECODE_B, "0b000"), 3);
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tg.config.add_enum(ebr + ".REGMODE_A", str_or_default(ci->params, id_REGMODE_A, "NOREG"));
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tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
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tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
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tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE", str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
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tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
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tg.config.add_word(ebr + ".WID", int_to_bitvector(int_or_default(ci->attrs, id_WID, 0), 9));
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// Invert CSDECODE bits to emulate inversion muxes on CSA/CSB signals
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for (auto &port : {std::make_pair("CSA", std::ref(csd_a)), std::make_pair("CSB", std::ref(csd_b))}) {
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for (int bit = 0; bit < 3; bit++) {
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std::string sig = port.first + std::to_string(bit);
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if (str_or_default(ci->params, ctx->id(sig + "MUX"), sig) == "INV")
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port.second.at(bit) = !port.second.at(bit);
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}
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}
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tg.config.add_enum(ebr + ".RSTAMUX", str_or_default(ci->params, id_RSTAMUX, "RSTA"));
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tg.config.add_enum(ebr + ".RSTBMUX", str_or_default(ci->params, id_RSTBMUX, "RSTB"));
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if (!ci->ramInfo.is_pdp) {
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tg.config.add_enum(ebr + ".WEAMUX", str_or_default(ci->params, id_WEAMUX, "WEA"));
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tg.config.add_enum(ebr + ".WEBMUX", str_or_default(ci->params, id_WEBMUX, "WEB"));
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}
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std::reverse(csd_a.begin(), csd_a.end());
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std::reverse(csd_b.begin(), csd_b.end());
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tg.config.add_word(ebr + ".CSDECODE_A", csd_a);
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tg.config.add_word(ebr + ".CSDECODE_B", csd_b);
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std::vector<uint16_t> init_data;
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init_data.resize(1024, 0x0);
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// INIT_00 .. INIT_1F
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for (int i = 0; i <= 0x1F; i++) {
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IdString param = ctx->idf("INITVAL_%02X", i);
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auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
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for (int j = 0; j < 16; j++) {
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// INIT parameter consists of 16 18-bit words with 2-bit padding
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int ofs = 20 * j;
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for (int k = 0; k < 18; k++) {
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if (value.at(ofs + k))
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init_data.at(i * 32 + j * 2 + (k / 9)) |= (1 << (k % 9));
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}
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}
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}
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int wid = int_or_default(ci->attrs, id_WID, 0);
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NPNR_ASSERT(!cc.bram_data.count(wid));
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cc.bram_data[wid] = init_data;
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cc.tilegroups.push_back(tg);
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}
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void write_pll(CellInfo *ci)
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void write_pll(CellInfo *ci)
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{
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{
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TileGroup tg;
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TileGroup tg;
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@ -543,6 +677,8 @@ struct MachXO2Bitgen
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cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
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cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq);
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} else if (ci->type == id_DCCA) {
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} else if (ci->type == id_DCCA) {
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write_dcc(ci);
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write_dcc(ci);
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} else if (ci->type == id_DP8KC) {
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write_bram(ci);
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} else if (ci->type == id_EHXPLLJ) {
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} else if (ci->type == id_EHXPLLJ) {
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write_pll(ci);
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write_pll(ci);
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}
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}
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114
machxo2/pack.cc
114
machxo2/pack.cc
@ -1012,6 +1012,107 @@ class MachXO2Packer
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}
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}
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}
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}
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// Pack EBR
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void pack_ebr()
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{
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// Autoincrement WID (starting from 3 seems to match vendor behaviour?)
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int wid = 3;
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auto rename_bus = [&](CellInfo *c, const std::string &oldname, const std::string &newname, int width,
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int oldoffset, int newoffset) {
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for (int i = 0; i < width; i++)
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c->renamePort(ctx->id(oldname + std::to_string(i + oldoffset)),
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ctx->id(newname + std::to_string(i + newoffset)));
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};
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auto rename_param = [&](CellInfo *c, const std::string &oldname, const std::string &newname) {
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IdString o = ctx->id(oldname), n = ctx->id(newname);
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if (!c->params.count(o))
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return;
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c->params[n] = c->params[o];
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c->params.erase(o);
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};
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/*for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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// Convert 36-bit PDP RAMs to regular 18-bit DP ones that match the Bel
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if (ci->type == id_PDPW8KC) {
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ci->params[id_DATA_WIDTH_A] = 18; // force PDP mode
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ci->params.erase(id_DATA_WIDTH_W);
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rename_bus(ci, "BE", "ADA", 4, 0, 0);
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rename_bus(ci, "ADW", "ADA", 9, 0, 5);
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rename_bus(ci, "ADR", "ADB", 14, 0, 0);
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rename_bus(ci, "CSW", "CSA", 3, 0, 0);
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rename_bus(ci, "CSR", "CSB", 3, 0, 0);
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rename_bus(ci, "DI", "DIA", 18, 0, 0);
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rename_bus(ci, "DI", "DIB", 18, 18, 0);
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rename_bus(ci, "DO", "DOA", 18, 18, 0);
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rename_bus(ci, "DO", "DOB", 18, 0, 0);
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ci->renamePort(id_CLKW, id_CLKA);
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ci->renamePort(id_CLKR, id_CLKB);
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ci->renamePort(id_CEW, id_CEA);
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ci->renamePort(id_CER, id_CEB);
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ci->renamePort(id_OCER, id_OCEB);
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rename_param(ci, "CLKWMUX", "CLKAMUX");
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if (str_or_default(ci->params, id_CLKAMUX) == "CLKW")
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ci->params[id_CLKAMUX] = std::string("CLKA");
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rename_param(ci, "CLKRMUX", "CLKBMUX");
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if (str_or_default(ci->params, id_CLKBMUX) == "CLKR")
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ci->params[id_CLKBMUX] = std::string("CLKB");
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rename_param(ci, "CSDECODE_W", "CSDECODE_A");
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rename_param(ci, "CSDECODE_R", "CSDECODE_B");
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std::string outreg = str_or_default(ci->params, id_REGMODE, "NOREG");
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ci->params[id_REGMODE_A] = outreg;
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ci->params[id_REGMODE_B] = outreg;
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ci->params.erase(id_REGMODE);
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rename_param(ci, "DATA_WIDTH_R", "DATA_WIDTH_B");
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if (ci->ports.count(id_RST)) {
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autocreate_empty_port(ci, id_RSTA);
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autocreate_empty_port(ci, id_RSTB);
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NetInfo *rst = ci->ports.at(id_RST).net;
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ci->connectPort(id_RSTA, rst);
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ci->connectPort(id_RSTB, rst);
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ci->disconnectPort(id_RST);
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ci->ports.erase(id_RST);
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}
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ci->type = id_DP8KC;
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}
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}*/
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (ci->type == id_DP8KC) {
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// Add ports, even if disconnected, to ensure correct tie-offs
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for (int i = 0; i < 13; i++) {
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autocreate_empty_port(ci, ctx->id("ADA" + std::to_string(i)));
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autocreate_empty_port(ci, ctx->id("ADB" + std::to_string(i)));
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}
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for (int i = 0; i < 9; i++) {
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autocreate_empty_port(ci, ctx->id("DIA" + std::to_string(i)));
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autocreate_empty_port(ci, ctx->id("DIB" + std::to_string(i)));
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}
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for (int i = 0; i < 3; i++) {
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autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
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autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
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}
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for (int i = 0; i < 3; i++) {
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autocreate_empty_port(ci, ctx->id("CSA" + std::to_string(i)));
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autocreate_empty_port(ci, ctx->id("CSB" + std::to_string(i)));
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}
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autocreate_empty_port(ci, id_CLKA);
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autocreate_empty_port(ci, id_CEA);
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autocreate_empty_port(ci, id_OCEA);
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autocreate_empty_port(ci, id_WEA);
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autocreate_empty_port(ci, id_RSTA);
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autocreate_empty_port(ci, id_CLKB);
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autocreate_empty_port(ci, id_CEB);
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autocreate_empty_port(ci, id_OCEB);
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autocreate_empty_port(ci, id_WEB);
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autocreate_empty_port(ci, id_RSTB);
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ci->attrs[id_WID] = wid++;
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}
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}
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}
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// Preplace PLL
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// Preplace PLL
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void preplace_plls()
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void preplace_plls()
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{
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{
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@ -1408,6 +1509,7 @@ class MachXO2Packer
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print_logic_usage();
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print_logic_usage();
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pack_io();
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pack_io();
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preplace_plls();
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preplace_plls();
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pack_ebr();
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pack_constants();
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pack_constants();
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pack_dram();
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pack_dram();
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pack_carries();
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pack_carries();
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@ -1510,6 +1612,18 @@ void Arch::assign_arch_info_for_cell(CellInfo *ci)
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ci->ffInfo.clk_sig = get_port_net(ci, id_CLK);
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ci->ffInfo.clk_sig = get_port_net(ci, id_CLK);
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ci->ffInfo.ce_sig = get_port_net(ci, id_CE);
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ci->ffInfo.ce_sig = get_port_net(ci, id_CE);
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ci->ffInfo.lsr_sig = get_port_net(ci, id_LSR);
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ci->ffInfo.lsr_sig = get_port_net(ci, id_LSR);
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} else if (ci->type == id_DP8KC) {
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ci->ramInfo.is_pdp = (int_or_default(ci->params, id_DATA_WIDTH_A, 0) == 18);
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// Output register mode (REGMODE_{A,B}). Valid options are 'NOREG' and 'OUTREG'.
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std::string regmode_a = str_or_default(ci->params, id_REGMODE_A, "NOREG");
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if (regmode_a != "NOREG" && regmode_a != "OUTREG")
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|
log_error("DP8KC %s has invalid REGMODE_A configuration '%s'\n", ci->name.c_str(this), regmode_a.c_str());
|
||||||
|
std::string regmode_b = str_or_default(ci->params, id_REGMODE_B, "NOREG");
|
||||||
|
if (regmode_b != "NOREG" && regmode_b != "OUTREG")
|
||||||
|
log_error("DP8KC %s has invalid REGMODE_B configuration '%s'\n", ci->name.c_str(this), regmode_b.c_str());
|
||||||
|
ci->ramInfo.is_output_a_registered = regmode_a == "OUTREG";
|
||||||
|
ci->ramInfo.is_output_b_registered = regmode_b == "OUTREG";
|
||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|||||||
Loading…
Reference in New Issue
Block a user