caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Fix delay prediction

Browse Source
This commit is contained in:
Eddie Hung 2018-12-06 17:40:15 -08:00
parent 904860b2b4
commit 8c44888466
3 changed files with 29 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

28
xc7/arch.cc
View File

@ -57,6 +57,16 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
{
static const boost::regex re_loc(".+_X(\\d+)Y(\\d+)");
boost::cmatch what;
tile_to_xy.resize(tiles.getTileCount());
for (TileIndex tileIndex(0); tileIndex < tiles.getTileCount(); tileIndex++) {
const auto &tileInfo = tiles.getTileInfo(tileIndex);
if (!boost::regex_match(tileInfo.getName(), what, re_loc))
throw;
const auto x = boost::lexical_cast<int>(what.str(1));
const auto y = boost::lexical_cast<int>(what.str(2));
tile_to_xy[tileIndex] = std::make_pair(x,y);
}
bel_to_site_index.reserve(sites.getSiteCount() * 4);
bel_to_loc.reserve(sites.getSiteCount() * 4);
site_index_to_bel.resize(sites.getSiteCount());
@ -67,11 +77,8 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
const auto &site = sites.getSite(i);
const auto &pd = site.getPrimitiveDefPtr();
const auto &type = pd->getName();
const auto &tileInfo = tiles.getTileInfo(site.getTileIndex());
if (!boost::regex_match(tileInfo.getName(), what, re_loc))
throw;
const auto x = boost::lexical_cast<int>(what.str(1));
const auto y = boost::lexical_cast<int>(what.str(2));
int x, y;
std::tie(x,y) = tile_to_xy[site.getTileIndex()];
if (type == "SLICEL" || type == "SLICEM") {
bel_to_site_index.push_back(i);
@ -129,8 +136,8 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
const boost::regex re_BOUNCE_NS("(BYP|FAN)_BOUNCE_[NS]3_\\d");
const boost::regex re_FAN("FAN(_ALT)?\\d");
const boost::regex re_CLB_I1_6("CLBL[LM]_(L|LL|M)_[A-D]([1-6])");
const boost::regex bufg_i("(CMT|CLK)_BUFG_BUFGCTRL\\d+_I0");
const boost::regex bufg_o("(CMT|CLK)_BUFG_BUFGCTRL\\d+_O");
const boost::regex bufg_i("CLK_BUFG_BUFGCTRL\\d+_I0");
const boost::regex bufg_o("CLK_BUFG_BUFGCTRL\\d+_O");
const boost::regex int_clk("CLK(_L)?[01]");
const boost::regex gclk("GCLK_(L_)?B\\d+(_EAST|_WEST)?");
std::unordered_map</*TileTypeIndex*/ unsigned, std::vector<delay_t>> delay_lookup;
@ -234,7 +241,7 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
wire_to_tilewire.shrink_to_fit();
wire_to_delay.shrink_to_fit();
num_wires = wire_to_tilewire.size();
wire_is_clk.resize(num_wires);
wire_is_global.resize(num_wires);
wire_to_pips_downhill.resize(num_wires);
// std::unordered_map<Arc, int> arc_to_pip;
@ -262,8 +269,9 @@ TorcInfo::TorcInfo(BaseCtx *ctx, const std::string &inDeviceName, const std::str
const bool clk_tile = boost::starts_with(tileTypeName, "CLK");
const bool int_tile = boost::starts_with(tileTypeName, "INT");
if (clk_tile)
wire_is_clk[w.index] = clk_tile;
const bool global_tile = boost::starts_with(tileTypeName, "CLK") || boost::starts_with(tileTypeName, "HCLK") || boost::starts_with(tileTypeName, "CFG");
if (global_tile)
wire_is_global[w.index] = true;
for (const auto &a : arcs) {
// Disable BUFG I0 -> O routethrough

6
xc7/arch.h
View File

@ -324,7 +324,8 @@ struct TorcInfo
std::vector<WireId> pip_to_dst_wire;
int width;
int height;
std::vector<bool> wire_is_clk;
std::vector<bool> wire_is_global;
std::vector<std::pair<int,int>> tile_to_xy;
TorcInfo(const std::string &inDeviceName, const std::string &inPackageName);
private:
@ -348,7 +349,8 @@ private:
ar & pip_to_arc;
ar & num_pips;
ar & pip_to_dst_wire;
ar & wire_is_clk;
ar & wire_is_global;
ar & tile_to_xy;
}
};
extern std::unique_ptr<const TorcInfo> torc_info;

22
xc7/delay.cc
View File

@ -101,14 +101,13 @@ void ice40DelayFuzzerMain(Context *ctx)
delay_t Arch::estimateDelay(WireId src, WireId dst) const
{
const auto &src_tw = torc_info->wire_to_tilewire[src.index];
const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
const auto &src_loc = torc_info->tile_to_xy[src_tw.getTileIndex()];
const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
const auto &dst_loc = torc_info->tile_to_xy[dst_tw.getTileIndex()];
if (!torc_info->wire_is_clk[src.index]) {
auto abs_delta_x = abs(src_info.getCol() - dst_info.getCol());
auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
#if 1
if (!torc_info->wire_is_global[src.index] || torc_info->wire_is_global[dst.index]) {
auto abs_delta_x = abs(dst_loc.first - src_loc.first);
auto abs_delta_y = abs(dst_loc.second - src_loc.second);
auto div_LH = std::div(abs_delta_x, 12);
auto div_LV = std::div(abs_delta_y, 18);
auto div_LVB = std::div(div_LV.rem, 12);
@ -123,13 +122,10 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
(div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
(num_H1 + num_V1) * 150;
#else
return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
#endif
}
else {
auto src_y = src_info.getRow();
auto dst_y = dst_info.getRow();
auto src_y = src_loc.second;
auto dst_y = dst_loc.second;
src_y -= src_y % 50;
dst_y -= dst_y % 50;
auto abs_delta_y = abs(src_y - dst_y);
@ -144,7 +140,6 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
auto sink_loc = getBelLocation(sink.cell->bel);
auto abs_delta_x = abs(driver_loc.x - sink_loc.x);
auto abs_delta_y = abs(driver_loc.y - sink_loc.y);
#if 1
auto div_LH = std::div(abs_delta_x, 12);
auto div_LV = std::div(abs_delta_y, 18);
auto div_LVB = std::div(div_LV.rem, 12);
@ -159,9 +154,6 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
(div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
(num_H1 + num_V1) * 150;
#else
return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
#endif
}
NEXTPNR_NAMESPACE_END