diff --git a/machxo2/arch.cc b/machxo2/arch.cc index c2b2e0ad..21129f07 100644 --- a/machxo2/arch.cc +++ b/machxo2/arch.cc @@ -109,7 +109,7 @@ Arch::Arch(ArchArgs args) : args(args) } } -bool Arch::isAvailable(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; } +bool Arch::is_available(ArchArgs::ArchArgsTypes chip) { return get_chip_info(chip) != nullptr; } std::string Arch::getChipName() const { @@ -130,7 +130,7 @@ std::string Arch::getChipName() const } } -std::string Arch::getFullChipName() const +std::string Arch::get_full_chip_name() const { std::string name = getChipName(); name += "-"; @@ -187,7 +187,7 @@ BelId Arch::getBelByName(IdStringList name) const loc.x = id_to_x.at(name[0]); loc.y = id_to_y.at(name[1]); ret.location = loc; - const TileTypePOD *loci = tileInfo(ret); + const TileTypePOD *loci = tile_info(ret); for (int i = 0; i < loci->num_bels; i++) { if (std::strcmp(loci->bel_data[i].name.get(), name[2].c_str(this)) == 0) { ret.index = i; @@ -207,7 +207,7 @@ BelId Arch::getBelByLocation(Loc loc) const ret.location.x = loc.x; ret.location.y = loc.y; - const TileTypePOD *tilei = tileInfo(ret); + const TileTypePOD *tilei = tile_info(ret); for (int i = 0; i < tilei->num_bels; i++) { if (tilei->bel_data[i].z == loc.z) { ret.index = i; @@ -241,8 +241,8 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const { NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tileInfo(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tileInfo(bel)->bel_data[bel.index].bel_wires; + int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; for (int i = 0; i < num_bel_wires; i++) if (bel_wires[i].port == pin.index) { @@ -262,8 +262,8 @@ PortType Arch::getBelPinType(BelId bel, IdString pin) const { NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tileInfo(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tileInfo(bel)->bel_data[bel.index].bel_wires; + int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; for (int i = 0; i < num_bel_wires; i++) if (bel_wires[i].port == pin.index) @@ -277,8 +277,8 @@ std::vector Arch::getBelPins(BelId bel) const std::vector ret; NPNR_ASSERT(bel != BelId()); - int num_bel_wires = tileInfo(bel)->bel_data[bel.index].num_bel_wires; - const BelWirePOD *bel_wires = &*tileInfo(bel)->bel_data[bel.index].bel_wires; + int num_bel_wires = tile_info(bel)->bel_data[bel.index].num_bel_wires; + const BelWirePOD *bel_wires = &*tile_info(bel)->bel_data[bel.index].bel_wires; for (int i = 0; i < num_bel_wires; i++) { IdString id(bel_wires[i].port); @@ -314,7 +314,7 @@ WireId Arch::getWireByName(IdStringList name) const loc.x = id_to_x.at(name[0]); loc.y = id_to_y.at(name[1]); ret.location = loc; - const TileTypePOD *loci = tileInfo(ret); + const TileTypePOD *loci = tile_info(ret); for (int i = 0; i < loci->num_wires; i++) { if (std::strcmp(loci->wire_data[i].name.get(), name[2].c_str(this)) == 0) { ret.index = i; @@ -340,7 +340,7 @@ PipId Arch::getPipByName(IdStringList name) const loc.x = id_to_x.at(name[0]); loc.y = id_to_y.at(name[1]); ret.location = loc; - const TileTypePOD *loci = tileInfo(ret); + const TileTypePOD *loci = tile_info(ret); for (int i = 0; i < loci->num_pips; i++) { PipId curr; curr.location = loc; @@ -354,10 +354,10 @@ PipId Arch::getPipByName(IdStringList name) const IdStringList Arch::getPipName(PipId pip) const { - auto &pip_data = tileInfo(pip)->pips_data[pip.index]; + auto &pip_data = tile_info(pip)->pips_data[pip.index]; WireId src = getPipSrcWire(pip), dst = getPipDstWire(pip); - const char *src_name = tileInfo(src)->wire_data[src.index].name.get(); - const char *dst_name = tileInfo(dst)->wire_data[dst.index].name.get(); + const char *src_name = tile_info(src)->wire_data[src.index].name.get(); + const char *dst_name = tile_info(dst)->wire_data[dst.index].name.get(); std::string pip_name = stringf("%d_%d_%s->%d_%d_%s", pip_data.src.x - pip.location.x, pip_data.src.y - pip.location.y, src_name, pip_data.dst.x - pip.location.x, pip_data.dst.y - pip.location.y, dst_name); @@ -465,9 +465,9 @@ const std::vector Arch::availablePlacers = {"sa", const std::string Arch::defaultRouter = "router1"; const std::vector Arch::availableRouters = {"router1", "router2"}; -bool Arch::cellsCompatible(const CellInfo **cells, int count) const { return false; } +bool Arch::cells_compatible(const CellInfo **cells, int count) const { return false; } -std::vector> Arch::getTilesAtLocation(int row, int col) +std::vector> Arch::get_tiles_at_location(int row, int col) { std::vector> ret; auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; diff --git a/machxo2/arch.h b/machxo2/arch.h index fae7523e..937157f3 100644 --- a/machxo2/arch.h +++ b/machxo2/arch.h @@ -406,12 +406,12 @@ struct Arch : BaseArch std::unordered_map id_to_x, id_to_y; // Helpers - template const TileTypePOD *tileInfo(Id &id) const + template const TileTypePOD *tile_info(Id &id) const { return &(chip_info->tiles[id.location.y * chip_info->width + id.location.x]); } - int getBelFlatIndex(BelId bel) const + int get_bel_flat_index(BelId bel) const { return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index; } @@ -423,11 +423,11 @@ struct Arch : BaseArch ArchArgs args; Arch(ArchArgs args); - static bool isAvailable(ArchArgs::ArchArgsTypes chip); + static bool is_available(ArchArgs::ArchArgsTypes chip); std::string getChipName() const override; // Extra helper - std::string getFullChipName() const; + std::string get_full_chip_name() const; IdString archId() const override { return id("machxo2"); } ArchArgs archArgs() const override { return args; } @@ -451,7 +451,7 @@ struct Arch : BaseArch { NPNR_ASSERT(bel != BelId()); std::array ids{x_ids.at(bel.location.x), y_ids.at(bel.location.y), - id(tileInfo(bel)->bel_data[bel.index].name.get())}; + id(tile_info(bel)->bel_data[bel.index].name.get())}; return IdStringList(ids); } @@ -461,7 +461,7 @@ struct Arch : BaseArch Loc loc; loc.x = bel.location.x; loc.y = bel.location.y; - loc.z = tileInfo(bel)->bel_data[bel.index].z; + loc.z = tile_info(bel)->bel_data[bel.index].z; return loc; } @@ -486,7 +486,7 @@ struct Arch : BaseArch { NPNR_ASSERT(bel != BelId()); IdString id; - id.index = tileInfo(bel)->bel_data[bel.index].type; + id.index = tile_info(bel)->bel_data[bel.index].type; return id; } @@ -504,7 +504,7 @@ struct Arch : BaseArch { NPNR_ASSERT(wire != WireId()); std::array ids{x_ids.at(wire.location.x), y_ids.at(wire.location.y), - id(tileInfo(wire)->wire_data[wire.index].name.get())}; + id(tile_info(wire)->wire_data[wire.index].name.get())}; return IdStringList(ids); } @@ -527,9 +527,9 @@ struct Arch : BaseArch { BelPinRange range; NPNR_ASSERT(wire != WireId()); - range.b.ptr = tileInfo(wire)->wire_data[wire.index].bel_pins.get(); + range.b.ptr = tile_info(wire)->wire_data[wire.index].bel_pins.get(); range.b.wire_loc = wire.location; - range.e.ptr = range.b.ptr + tileInfo(wire)->wire_data[wire.index].num_bel_pins; + range.e.ptr = range.b.ptr + tile_info(wire)->wire_data[wire.index].num_bel_pins; range.e.wire_loc = wire.location; return range; } @@ -567,8 +567,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tileInfo(pip)->pips_data[pip.index].src_idx; - wire.location = tileInfo(pip)->pips_data[pip.index].src; + wire.index = tile_info(pip)->pips_data[pip.index].src_idx; + wire.location = tile_info(pip)->pips_data[pip.index].src; return wire; } @@ -576,8 +576,8 @@ struct Arch : BaseArch { WireId wire; NPNR_ASSERT(pip != PipId()); - wire.index = tileInfo(pip)->pips_data[pip.index].dst_idx; - wire.location = tileInfo(pip)->pips_data[pip.index].dst; + wire.index = tile_info(pip)->pips_data[pip.index].dst_idx; + wire.location = tile_info(pip)->pips_data[pip.index].dst; return wire; } @@ -594,9 +594,9 @@ struct Arch : BaseArch { PipRange range; NPNR_ASSERT(wire != WireId()); - range.b.cursor = tileInfo(wire)->wire_data[wire.index].pips_downhill.get(); + range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_downhill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tileInfo(wire)->wire_data[wire.index].num_downhill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_downhill; range.e.wire_loc = wire.location; return range; } @@ -605,21 +605,21 @@ struct Arch : BaseArch { PipRange range; NPNR_ASSERT(wire != WireId()); - range.b.cursor = tileInfo(wire)->wire_data[wire.index].pips_uphill.get(); + range.b.cursor = tile_info(wire)->wire_data[wire.index].pips_uphill.get(); range.b.wire_loc = wire.location; - range.e.cursor = range.b.cursor + tileInfo(wire)->wire_data[wire.index].num_uphill; + range.e.cursor = range.b.cursor + tile_info(wire)->wire_data[wire.index].num_uphill; range.e.wire_loc = wire.location; return range; } // Extra Pip helpers. - int8_t getPipClass(PipId pip) const { return tileInfo(pip)->pips_data[pip.index].pip_type; } + int8_t get_pip_class(PipId pip) const { return tile_info(pip)->pips_data[pip.index].pip_type; } - std::string getPipTilename(PipId pip) const + std::string get_pip_tilename(PipId pip) const { auto &tileloc = chip_info->tile_info[pip.location.y * chip_info->width + pip.location.x]; for (int i = 0; i < tileloc.num_tiles; i++) { - if (tileloc.tile_names[i].type_idx == tileInfo(pip)->pips_data[pip.index].tile_type) + if (tileloc.tile_names[i].type_idx == tile_info(pip)->pips_data[pip.index].tile_type) return tileloc.tile_names[i].name.get(); } NPNR_ASSERT_FALSE("failed to find Pip tile"); @@ -659,10 +659,10 @@ struct Arch : BaseArch // --------------------------------------------------------------- // Internal usage - bool cellsCompatible(const CellInfo **cells, int count) const; + bool cells_compatible(const CellInfo **cells, int count) const; - std::vector> getTilesAtLocation(int row, int col); - std::string getTileByTypeAndLocation(int row, int col, std::string type) const + std::vector> get_tiles_at_location(int row, int col); + std::string get_tile_by_type_and_loc(int row, int col, std::string type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; for (int i = 0; i < tileloc.num_tiles; i++) { @@ -673,7 +673,7 @@ struct Arch : BaseArch type); } - std::string getTileByTypeAndLocation(int row, int col, const std::set &type) const + std::string get_tile_by_type_and_loc(int row, int col, const std::set &type) const { auto &tileloc = chip_info->tile_info[row * chip_info->width + col]; for (int i = 0; i < tileloc.num_tiles; i++) { @@ -683,7 +683,7 @@ struct Arch : BaseArch NPNR_ASSERT_FALSE_STR("no tile at (" + std::to_string(col) + ", " + std::to_string(row) + ") with type in set"); } - std::string getTileByType(std::string type) const + std::string get_tile_by_type(std::string type) const { for (int i = 0; i < chip_info->height * chip_info->width; i++) { auto &tileloc = chip_info->tile_info[i]; diff --git a/machxo2/bitstream.cc b/machxo2/bitstream.cc index 1711326f..37363b09 100644 --- a/machxo2/bitstream.cc +++ b/machxo2/bitstream.cc @@ -52,7 +52,7 @@ void config_empty_lcmxo2_1200hc(ChipConfig &cc) // Convert an absolute wire name to a relative Trellis one static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) { - std::string basename = ctx->tileInfo(wire)->wire_data[wire.index].name.get(); + std::string basename = ctx->tile_info(wire)->wire_data[wire.index].name.get(); std::string prefix2 = basename.substr(0, 2); std::string prefix7 = basename.substr(0, 7); int max_col = ctx->chip_info->width - 1; @@ -99,7 +99,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) static void set_pip(Context *ctx, ChipConfig &cc, PipId pip) { - std::string tile = ctx->getPipTilename(pip); + std::string tile = ctx->get_pip_tilename(pip); std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); cc.tiles[tile].add_arc(sink, source); @@ -148,15 +148,15 @@ static std::string get_pic_tile(Context *ctx, BelId bel) static const std::set pio_l = {"PIC_L0", "PIC_LS0", "PIC_L0_VREF3"}; static const std::set pio_r = {"PIC_R0", "PIC_RS0"}; - std::string pio_name = ctx->tileInfo(bel)->bel_data[bel.index].name.get(); + std::string pio_name = ctx->tile_info(bel)->bel_data[bel.index].name.get(); if (bel.location.y == 0) { - return ctx->getTileByTypeAndLocation(0, bel.location.x, "PIC_T0"); + return ctx->get_tile_by_type_and_loc(0, bel.location.x, "PIC_T0"); } else if (bel.location.y == ctx->chip_info->height - 1) { - return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, "PIC_B0"); + return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PIC_B0"); } else if (bel.location.x == 0) { - return ctx->getTileByTypeAndLocation(bel.location.y, 0, pio_l); + return ctx->get_tile_by_type_and_loc(bel.location.y, 0, pio_l); } else if (bel.location.x == ctx->chip_info->width - 1) { - return ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, pio_r); + return ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, pio_r); } else { NPNR_ASSERT_FALSE("bad PIO location"); } @@ -174,12 +174,12 @@ void write_bitstream(Context *ctx, std::string text_config_file) NPNR_ASSERT_FALSE("Unsupported device type"); } - cc.metadata.push_back("Part: " + ctx->getFullChipName()); + cc.metadata.push_back("Part: " + ctx->get_full_chip_name()); // Add all set, configurable pips to the config for (auto pip : ctx->getPips()) { if (ctx->getBoundPipNet(pip) != nullptr) { - if (ctx->getPipClass(pip) == 0) { // ignore fixed pips + if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips set_pip(ctx, cc, pip); } } @@ -197,8 +197,8 @@ void write_bitstream(Context *ctx, std::string text_config_file) } BelId bel = ci->bel; if (ci->type == id_FACADE_SLICE) { - std::string tname = ctx->getTileByTypeAndLocation(bel.location.y, bel.location.x, "PLC"); - std::string slice = ctx->tileInfo(bel)->bel_data[bel.index].name.get(); + std::string tname = ctx->get_tile_by_type_and_loc(bel.location.y, bel.location.x, "PLC"); + std::string slice = ctx->tile_info(bel)->bel_data[bel.index].name.get(); NPNR_ASSERT(slice.substr(0, 5) == "SLICE"); int int_index = slice[5] - 'A'; @@ -227,15 +227,15 @@ void write_bitstream(Context *ctx, std::string text_config_file) cc.tiles[tname].add_enum(slice + ".REG1.REGSET", str_or_default(ci->params, ctx->id("REG1_REGSET"), "RESET")); } else if (ci->type == ctx->id("FACADE_IO")) { - std::string pio = ctx->tileInfo(bel)->bel_data[bel.index].name.get(); + std::string pio = ctx->tile_info(bel)->bel_data[bel.index].name.get(); std::string iotype = str_or_default(ci->attrs, ctx->id("IO_TYPE"), "LVCMOS33"); std::string dir = str_or_default(ci->params, ctx->id("DIR"), "INPUT"); std::string pic_tile = get_pic_tile(ctx, bel); cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); } else if (ci->type == ctx->id("OSCH")) { std::string freq = str_or_default(ci->params, ctx->id("NOM_FREQ"), "2.08"); - cc.tiles[ctx->getTileByType("CFG1")].add_enum("OSCH.MODE", "OSCH"); - cc.tiles[ctx->getTileByType("CFG1")].add_enum("OSCH.NOM_FREQ", freq); + cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.MODE", "OSCH"); + cc.tiles[ctx->get_tile_by_type("CFG1")].add_enum("OSCH.NOM_FREQ", freq); } } diff --git a/machxo2/main.cc b/machxo2/main.cc index 3d0884bf..961fe9ae 100644 --- a/machxo2/main.cc +++ b/machxo2/main.cc @@ -47,17 +47,17 @@ MachXO2CommandHandler::MachXO2CommandHandler(int argc, char **argv) : CommandHan po::options_description MachXO2CommandHandler::getArchOptions() { po::options_description specific("Architecture specific options"); - if (Arch::isAvailable(ArchArgs::LCMXO2_256HC)) + if (Arch::is_available(ArchArgs::LCMXO2_256HC)) specific.add_options()("256", "set device type to LCMXO2-256HC"); - if (Arch::isAvailable(ArchArgs::LCMXO2_640HC)) + if (Arch::is_available(ArchArgs::LCMXO2_640HC)) specific.add_options()("640", "set device type to LCMXO2-640HC"); - if (Arch::isAvailable(ArchArgs::LCMXO2_1200HC)) + if (Arch::is_available(ArchArgs::LCMXO2_1200HC)) specific.add_options()("1200", "set device type to LCMXO2-1200HC"); - if (Arch::isAvailable(ArchArgs::LCMXO2_2000HC)) + if (Arch::is_available(ArchArgs::LCMXO2_2000HC)) specific.add_options()("2000", "set device type to LCMXO2-2000HC"); - if (Arch::isAvailable(ArchArgs::LCMXO2_4000HC)) + if (Arch::is_available(ArchArgs::LCMXO2_4000HC)) specific.add_options()("4000", "set device type to LCMXO2-4000HC"); - if (Arch::isAvailable(ArchArgs::LCMXO2_7000HC)) + if (Arch::is_available(ArchArgs::LCMXO2_7000HC)) specific.add_options()("7000", "set device type to LCMXO2-7000HC"); specific.add_options()("package", po::value(), "select device package");