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Merge pull request #678 from acomodi/initial-fasm-generation

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interchange: add FASM generation target and clean-up tests
This commit is contained in:
gatecat 2021-04-14 14:28:01 +01:00 committed by GitHub
commit 8f5185c381
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GPG Key ID: 4AEE18F83AFDEB23
21 changed files with 136 additions and 71 deletions
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2
.github/workflows/interchange_ci.yml vendored
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@ -108,7 +108,7 @@ jobs:
env:
RAPIDWRIGHT_PATH: ${{ github.workspace }}/RapidWright
PYTHON_INTERCHANGE_PATH: ${{ github.workspace }}/python-fpga-interchange
PYTHON_INTERCHANGE_TAG: v0.0.7
PYTHON_INTERCHANGE_TAG: v0.0.9
PRJOXIDE_REVISION: a85135648c3ef2f7b3fd53ae2187ef6460e34b16
DEVICE: ${{ matrix.device }}
run: |

7
fpga_interchange/examples/boards.cmake
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@ -2,6 +2,7 @@ function(add_board)
# ~~~
# add_board(
# name <board name>
# device_family <device family>
# device <common device>
# package <package>
# )
@ -12,6 +13,8 @@ function(add_board)
#
# Arguments:
# - name: name of the board. E.g. arty
# - device_family: the name of the family this device belongs to.
# E.g. the xc7a35t device belongs to the xc7 family
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
# share the same xc7a35t device prefix
# - package: one of the packages available for a given device. E.g. cpg236
@ -20,7 +23,7 @@ function(add_board)
# - board-<name>
set(options)
set(oneValueArgs name device package)
set(oneValueArgs name device_family device package)
set(multiValueArgs)
cmake_parse_arguments(
@ -32,6 +35,7 @@ function(add_board)
)
set(name ${add_board_name})
set(device_family ${add_board_device_family})
set(device ${add_board_device})
set(package ${add_board_package})
@ -39,6 +43,7 @@ function(add_board)
set_target_properties(
board-${name}
PROPERTIES
DEVICE_FAMILY ${device_family}
DEVICE ${device}
PACKAGE ${package}
)

5
fpga_interchange/examples/boards/CMakeLists.txt
View File

@ -1,29 +1,34 @@
add_board(
name arty35t
device_family xc7
device xc7a35t
package csg324
)
add_board(
name arty100t
device_family xc7
device xc7a100t
package csg324
)
add_board(
name nexys_video
device_family xc7
device xc7a200t
package sbg484
)
add_board(
name basys3
device_family xc7
device xc7a35t
package cpg236
)
add_board(
name zybo
device_family xc7
device xc7z010
package clg400
)

63
fpga_interchange/examples/tests.cmake
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@ -10,6 +10,8 @@ function(add_interchange_test)
# sources <sources list>
# [top <top name>]
# [techmap <techmap file>]
# [output_fasm]
# [device_family <device family>]
# )
#
# Generates targets to run desired tests
@ -18,6 +20,8 @@ function(add_interchange_test)
# - name: test name. This must be unique and no other tests with the same
# name should exist
# - family: nextpnr architecture family (e.g. fpga_interchange)
# - device_family: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
# share the same xc7a35t device prefix
# - device: common device name of a set of parts. E.g. xc7a35tcsg324-1 and xc7a35tcpg236-1
# share the same xc7a35t device prefix
# - package: package among the ones available for the device
@ -27,6 +31,9 @@ function(add_interchange_test)
# - top (optional): name of the top level module.
# If not provided, "top" is assigned as top level module
# - techmap (optional): techmap file used during synthesis
# - output_fasm (optional): generates a fasm output
# - device_family (optional): this information is used during FASM generation, therfore it is
# required only if the `output_fasm` option is enabled
#
# Targets generated:
# - test-fpga_interchange-<name>-json : synthesis output
@ -34,8 +41,8 @@ function(add_interchange_test)
# - test-fpga_interchange-<name>-phys : interchange physical netlist
# - test-fpga_interchange-<name>-dcp : design checkpoint with RapidWright
set(options skip_dcp)
set(oneValueArgs name family device package tcl xdc top techmap)
set(options skip_dcp output_fasm)
set(oneValueArgs name family device package tcl xdc top techmap device_family)
set(multiValueArgs sources)
cmake_parse_arguments(
@ -51,10 +58,12 @@ function(add_interchange_test)
set(device ${add_interchange_test_device})
set(package ${add_interchange_test_package})
set(skip_dcp ${add_interchange_test_skip_dcp})
set(output_fasm ${add_interchange_test_output_fasm})
set(top ${add_interchange_test_top})
set(tcl ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_tcl})
set(xdc ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_xdc})
set(techmap ${CMAKE_CURRENT_SOURCE_DIR}/${add_interchange_test_techmap})
set(device_family ${add_interchange_test_device_family})
set(sources)
foreach(source ${add_interchange_test_sources})
@ -247,9 +256,9 @@ function(add_interchange_test)
add_custom_target(test-${family}-${name}-phys-yaml DEPENDS ${phys_yaml})
set(last_target "")
if(skip_dcp)
add_dependencies(all-${family}-tests test-${family}-${name}-phys-yaml)
add_dependencies(all-${device}-tests test-${family}-${name}-phys-yaml)
set(last_target test-${family}-${name}-phys)
else()
set(dcp ${CMAKE_CURRENT_BINARY_DIR}/${name}.dcp)
add_custom_command(
@ -266,8 +275,38 @@ function(add_interchange_test)
)
add_custom_target(test-${family}-${name}-dcp DEPENDS ${dcp})
add_dependencies(all-${family}-tests test-${family}-${name}-dcp)
add_dependencies(all-${device}-tests test-${family}-${name}-dcp)
set(last_target test-${family}-${name}-dcp)
endif()
add_dependencies(all-${device}-tests ${last_target})
add_dependencies(all-${family}-tests ${last_target})
if(output_fasm)
if(NOT DEFINED device_family)
message(FATAL_ERROR "If FASM output is enabled, the device family must be provided as well!")
endif()
# Output FASM target
set(fasm ${CMAKE_CURRENT_BINARY_DIR}/${name}.fasm)
add_custom_command(
OUTPUT ${fasm}
COMMAND
${PYTHON_EXECUTABLE} -mfpga_interchange.fasm_generator
--schema_dir ${INTERCHANGE_SCHEMA_PATH}
--family ${device_family}
${device_loc}
${netlist}
${phys}
${fasm}
DEPENDS
${device_target}
${netlist}
${phys}
)
add_custom_target(test-${family}-${name}-fasm DEPENDS ${fasm} ${last_target})
add_dependencies(all-${device}-tests test-${family}-${name}-fasm)
add_dependencies(all-${family}-tests test-${family}-${name}-fasm)
endif()
endfunction()
@ -301,7 +340,7 @@ function(add_interchange_group_test)
# Note: it is assumed that there exists an XDC file for each board, with the following naming
# convention: <board>.xdc
set(options)
set(options output_fasm)
set(oneValueArgs name family tcl top techmap)
set(multiValueArgs sources board_list)
@ -319,6 +358,13 @@ function(add_interchange_group_test)
set(tcl ${add_interchange_group_test_tcl})
set(techmap ${add_interchange_group_test_techmap})
set(sources ${add_interchange_group_test_sources})
set(output_fasm ${add_interchange_group_test_output_fasm})
set(output_fasm_arg "")
if(output_fasm)
set(output_fasm_arg "output_fasm")
endif()
if (NOT DEFINED top)
# Setting default top value
@ -326,6 +372,7 @@ function(add_interchange_group_test)
endif()
foreach(board ${add_interchange_group_test_board_list})
get_property(device_family TARGET board-${board} PROPERTY DEVICE_FAMILY)
get_property(device TARGET board-${board} PROPERTY DEVICE)
get_property(package TARGET board-${board} PROPERTY PACKAGE)
@ -333,12 +380,14 @@ function(add_interchange_group_test)
name ${name}_${board}
family ${family}
device ${device}
device_family ${device_family}
package ${package}
tcl ${tcl}
xdc ${board}.xdc
sources ${sources}
top ${top}
techmap ${techmap}
${output_fasm_arg}
)
endforeach()
endfunction()

18
fpga_interchange/examples/tests/const_wire/CMakeLists.txt
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@ -1,19 +1,7 @@
add_interchange_test(
name const_wire_basys3
add_interchange_group_test(
name const_wire
family ${family}
device xc7a35t
package cpg236
board_list basys3 arty35t arty100t
tcl run.tcl
xdc wire_basys3.xdc
sources wire.v
)
add_interchange_test(
name const_wire_arty
family ${family}
device xc7a35t
package csg324
tcl run.tcl
xdc wire_arty.xdc
sources wire.v
)

8
fpga_interchange/examples/tests/const_wire/wire_arty.xdc → fpga_interchange/examples/tests/const_wire/arty100t.xdc
View File

@ -1,7 +1,7 @@
set_property PACKAGE_PIN N15 [get_ports o]
set_property PACKAGE_PIN N16 [get_ports o2]
set_property PACKAGE_PIN P17 [get_ports o3]
set_property PACKAGE_PIN R17 [get_ports o4]
set_property PACKAGE_PIN H5 [get_ports o]
set_property PACKAGE_PIN J5 [get_ports o2]
set_property PACKAGE_PIN T9 [get_ports o3]
set_property PACKAGE_PIN T10 [get_ports o4]
set_property IOSTANDARD LVCMOS33 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports o2]

9
fpga_interchange/examples/tests/const_wire/arty35t.xdc Normal file
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@ -0,0 +1,9 @@
set_property PACKAGE_PIN H5 [get_ports o]
set_property PACKAGE_PIN J5 [get_ports o2]
set_property PACKAGE_PIN T9 [get_ports o3]
set_property PACKAGE_PIN T10 [get_ports o4]
set_property IOSTANDARD LVCMOS33 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports o2]
set_property IOSTANDARD LVCMOS33 [get_ports o3]
set_property IOSTANDARD LVCMOS33 [get_ports o4]

0
fpga_interchange/examples/tests/const_wire/wire_basys3.xdc → fpga_interchange/examples/tests/const_wire/basys3.xdc
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3
fpga_interchange/examples/tests/counter/CMakeLists.txt
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@ -1,8 +1,9 @@
add_interchange_group_test(
name counter
family ${family}
board_list basys3 arty35t arty100t
board_list basys3 arty35t arty100t zybo
tcl run.tcl
sources counter.v
techmap ../../remap.v
output_fasm
)

14
fpga_interchange/examples/tests/counter/zybo.xdc Normal file
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@ -0,0 +1,14 @@
# zybo board
set_property PACKAGE_PIN K17 [get_ports clk]
set_property PACKAGE_PIN K18 [get_ports rst]
set_property PACKAGE_PIN M14 [get_ports io_led[4]]
set_property PACKAGE_PIN M15 [get_ports io_led[5]]
set_property PACKAGE_PIN G14 [get_ports io_led[6]]
set_property PACKAGE_PIN D18 [get_ports io_led[7]]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports rst]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[4]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[5]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[6]]
set_property IOSTANDARD LVCMOS33 [get_ports io_led[7]]

19
fpga_interchange/examples/tests/ff/CMakeLists.txt
View File

@ -1,19 +1,8 @@
add_interchange_test(
name ff_basys3
add_interchange_group_test(
name ff
family ${family}
device xc7a35t
package cpg236
board_list basys3 arty35t arty100t
tcl run.tcl
xdc ff_basys3.xdc
sources ff.v
)
add_interchange_test(
name ff_arty
family ${family}
device xc7a35t
package csg324
tcl run.tcl
xdc ff_arty.xdc
sources ff.v
output_fasm
)

8
fpga_interchange/examples/tests/ff/ff_arty.xdc → fpga_interchange/examples/tests/ff/arty100t.xdc
View File

@ -1,7 +1,7 @@
set_property PACKAGE_PIN P17 [get_ports clk]
set_property PACKAGE_PIN N15 [get_ports d]
set_property PACKAGE_PIN N16 [get_ports r]
set_property PACKAGE_PIN M17 [get_ports q]
set_property PACKAGE_PIN E3 [get_ports clk]
set_property PACKAGE_PIN A8 [get_ports d]
set_property PACKAGE_PIN D9 [get_ports r]
set_property PACKAGE_PIN H5 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports d]

9
fpga_interchange/examples/tests/ff/arty35t.xdc Normal file
View File

@ -0,0 +1,9 @@
set_property PACKAGE_PIN E3 [get_ports clk]
set_property PACKAGE_PIN A8 [get_ports d]
set_property PACKAGE_PIN D9 [get_ports r]
set_property PACKAGE_PIN H5 [get_ports q]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property IOSTANDARD LVCMOS33 [get_ports d]
set_property IOSTANDARD LVCMOS33 [get_ports r]
set_property IOSTANDARD LVCMOS33 [get_ports q]

0
fpga_interchange/examples/tests/ff/ff_basys3.xdc → fpga_interchange/examples/tests/ff/basys3.xdc
View File

19
fpga_interchange/examples/tests/lut/CMakeLists.txt
View File

@ -1,19 +1,8 @@
add_interchange_test(
name lut_basys3
add_interchange_group_test(
name lut
family ${family}
device xc7a35t
package cpg236
board_list basys3 arty35t arty100t
tcl run.tcl
xdc lut_basys3.xdc
sources lut.v
)
add_interchange_test(
name lut_arty
family ${family}
device xc7a35t
package csg324
tcl run.tcl
xdc lut_arty.xdc
sources lut.v
output_fasm
)

6
fpga_interchange/examples/tests/lut/lut_arty.xdc → fpga_interchange/examples/tests/lut/arty100t.xdc
View File

@ -1,6 +1,6 @@
set_property PACKAGE_PIN N16 [get_ports i0]
set_property PACKAGE_PIN N15 [get_ports i1]
set_property PACKAGE_PIN M17 [get_ports o]
set_property PACKAGE_PIN A8 [get_ports i0]
set_property PACKAGE_PIN C11 [get_ports i1]
set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i0]
set_property IOSTANDARD LVCMOS33 [get_ports i1]

7
fpga_interchange/examples/tests/lut/arty35t.xdc Normal file
View File

@ -0,0 +1,7 @@
set_property PACKAGE_PIN A8 [get_ports i0]
set_property PACKAGE_PIN C11 [get_ports i1]
set_property PACKAGE_PIN H5 [get_ports o]
set_property IOSTANDARD LVCMOS33 [get_ports i0]
set_property IOSTANDARD LVCMOS33 [get_ports i1]
set_property IOSTANDARD LVCMOS33 [get_ports o]

0
fpga_interchange/examples/tests/lut/lut_basys3.xdc → fpga_interchange/examples/tests/lut/basys3.xdc
View File

8
fpga_interchange/examples/tests/ram/CMakeLists.txt
View File

@ -1,10 +1,8 @@
add_interchange_test(
name ram_basys3
add_interchange_group_test(
name ram
family ${family}
device xc7a35t
package cpg236
board_list basys3
tcl run.tcl
xdc basys3.xdc
sources ram.v
)

1
fpga_interchange/examples/tests/wire/CMakeLists.txt
View File

@ -4,4 +4,5 @@ add_interchange_group_test(
board_list basys3 arty35t zybo arty100t nexys_video
tcl run.tcl
sources wire.v
output_fasm
)

1
fpga_interchange/family.cmake
View File

@ -24,6 +24,7 @@ set(chipdb_dir ${CMAKE_CURRENT_BINARY_DIR}/${family}/chipdb)
file(MAKE_DIRECTORY ${chipdb_dir})
add_custom_target(all-${family}-tests)
add_custom_target(all-${family}-fasm)
add_custom_target(all-${family}-archcheck-tests)
add_subdirectory(${family}/examples/devices)
add_subdirectory(${family}/examples/boards)