nextpnr: Add base virtual functions for non-range Arch API
This makes the Arch API clearer and also allows a base implementation of functions to reduce the amount of complexity to get a basic Arch up and running. Currently this only implements these for functions that don't return a range. Range-returning functions will require more work in order due to the current 'duck typing' approach (probably a struct that contains the range types combined with templating.) Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
D. Shah
parent
8b4163b77c
commit
8f76af40db
108
common/nextpnr.h
108
common/nextpnr.h
@ -1006,6 +1006,114 @@ struct BaseCtx
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void archInfoToAttributes();
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void attributesToArchInfo();
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// --------------------------------------------------------------
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// Arch API base
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// Basic config
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virtual int getGridDimX() const = 0;
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virtual int getGridDimY() const = 0;
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virtual int getTileBelDimZ(int x, int y) const = 0;
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virtual int getTilePipDimZ(int x, int y) const { return 1; }
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virtual char getNameDelimiter() const { return ' '; }
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// Bel methods
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virtual BelId getBelByName(IdStringList name) const = 0;
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virtual IdStringList getBelName(BelId bel) const = 0;
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virtual uint32_t getBelChecksum(BelId bel) const { return uint32_t(std::hash<BelId>()(bel)); }
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virtual void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) = 0;
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virtual void unbindBel(BelId bel) = 0;
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virtual Loc getBelLocation(BelId bel) const = 0;
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virtual BelId getBelByLocation(Loc loc) const = 0;
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virtual bool getBelGlobalBuf(BelId bel) const { return false; }
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virtual bool checkBelAvail(BelId bel) const = 0;
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virtual CellInfo *getBoundBelCell(BelId bel) const = 0;
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virtual CellInfo *getConflictingBelCell(BelId bel) const = 0;
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virtual IdString getBelType(BelId bel) const = 0;
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virtual WireId getBelPinWire(BelId bel, IdString pin) const = 0;
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virtual PortType getBelPinType(BelId bel, IdString pin) const = 0;
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// Wire methods
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virtual WireId getWireByName(IdStringList name) const = 0;
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virtual IdStringList getWireName(WireId wire) const = 0;
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virtual IdString getWireType(WireId wire) const { return IdString(); }
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virtual uint32_t getWireChecksum(WireId wire) const { return uint32_t(std::hash<WireId>()(wire)); }
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virtual void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) = 0;
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virtual void unbindWire(WireId wire) = 0;
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virtual bool checkWireAvail(WireId wire) const = 0;
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virtual NetInfo *getBoundWireNet(WireId wire) const = 0;
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virtual WireId getConflictingWireWire(WireId wire) const { return wire; };
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virtual NetInfo *getConflictingWireNet(WireId wire) const { return getBoundWireNet(wire); }
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virtual DelayInfo getWireDelay(WireId wire) const = 0;
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// Pip methods
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virtual PipId getPipByName(IdStringList name) const = 0;
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virtual IdStringList getPipName(PipId pip) const = 0;
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virtual IdString getPipType(PipId pip) const { return IdString(); }
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virtual uint32_t getPipChecksum(PipId pip) const { return uint32_t(std::hash<PipId>()(pip)); }
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virtual void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) = 0;
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virtual void unbindPip(PipId pip) = 0;
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virtual bool checkPipAvail(PipId pip) const = 0;
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virtual NetInfo *getBoundPipNet(PipId pip) const = 0;
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virtual WireId getConflictingPipWire(PipId pip) const { return WireId(); }
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virtual NetInfo *getConflictingPipNet(PipId pip) const { return nullptr; }
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virtual WireId getPipSrcWire(PipId pip) const = 0;
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virtual WireId getPipDstWire(PipId pip) const = 0;
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virtual DelayInfo getPipDelay(PipId pip) const = 0;
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virtual Loc getPipLocation(PipId pip) const = 0;
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// Group methods
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virtual GroupId getGroupByName(IdStringList name) const = 0;
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virtual IdStringList getGroupName(GroupId group) const = 0;
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virtual delay_t estimateDelay(WireId src, WireId dst) const = 0;
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virtual ArcBounds getRouteBoundingBox(WireId src, WireId dst) const = 0;
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// Delay methods
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virtual delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const = 0;
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virtual delay_t getDelayEpsilon() const = 0;
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virtual delay_t getRipupDelayPenalty() const = 0;
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virtual float getDelayNS(delay_t v) const = 0;
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virtual DelayInfo getDelayFromNS(float ns) const = 0;
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virtual uint32_t getDelayChecksum(delay_t v) const = 0;
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virtual bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const
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{
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return false;
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}
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// Decal methods
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virtual DecalXY getBelDecal(BelId bel) const { return DecalXY(); }
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virtual DecalXY getWireDecal(WireId wire) const { return DecalXY(); }
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virtual DecalXY getPipDecal(PipId pip) const { return DecalXY(); }
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virtual DecalXY getGroupDecal(GroupId group) const { return DecalXY(); }
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// Cell timing methods
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virtual bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const
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{
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return false;
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}
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virtual TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const
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{
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return TMG_IGNORE;
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}
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virtual TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const
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{
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NPNR_ASSERT_FALSE("unreachable");
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}
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// Placement validity checks
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virtual bool isValidBelForCellType(IdString cell_type, BelId bel) const { return cell_type == getBelType(bel); }
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virtual IdString getBelBucketName(BelBucketId bucket) const = 0;
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virtual BelBucketId getBelBucketByName(IdString name) const = 0;
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virtual BelBucketId getBelBucketForBel(BelId bel) const = 0;
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virtual BelBucketId getBelBucketForCellType(IdString cell_type) const = 0;
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virtual bool isValidBelForCell(CellInfo *cell, BelId bel) const { return true; }
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virtual bool isBelLocationValid(BelId bel) const { return true; }
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// Flow methods
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virtual bool pack() = 0;
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virtual bool place() = 0;
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virtual bool route() = 0;
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virtual void assignArchInfo(){};
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};
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NEXTPNR_NAMESPACE_END
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152
ecp5/arch.h
152
ecp5/arch.h
@ -470,22 +470,22 @@ struct Arch : BaseCtx
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static const int max_loc_bels = 20;
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int getGridDimX() const { return chip_info->width; };
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int getGridDimY() const { return chip_info->height; };
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int getTileBelDimZ(int, int) const { return max_loc_bels; };
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int getTilePipDimZ(int, int) const { return 1; };
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char getNameDelimiter() const { return '/'; }
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int getGridDimX() const override { return chip_info->width; };
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int getGridDimY() const override { return chip_info->height; };
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int getTileBelDimZ(int, int) const override { return max_loc_bels; };
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int getTilePipDimZ(int, int) const override { return 1; };
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char getNameDelimiter() const override { return '/'; }
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// -------------------------------------------------
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BelId getBelByName(IdStringList name) const;
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BelId getBelByName(IdStringList name) const override;
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template <typename Id> const LocationTypePOD *loc_info(Id &id) const
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{
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return &(chip_info->locations[chip_info->location_type[id.location.y * chip_info->width + id.location.x]]);
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}
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IdStringList getBelName(BelId bel) const
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IdStringList getBelName(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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std::array<IdString, 3> ids{x_ids.at(bel.location.x), y_ids.at(bel.location.y),
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@ -493,14 +493,14 @@ struct Arch : BaseCtx
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return IdStringList(ids);
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}
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uint32_t getBelChecksum(BelId bel) const { return bel.index; }
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uint32_t getBelChecksum(BelId bel) const override { return bel.index; }
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int get_bel_flat_index(BelId bel) const
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{
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return (bel.location.y * chip_info->width + bel.location.x) * max_loc_bels + bel.index;
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}
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength)
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void bindBel(BelId bel, CellInfo *cell, PlaceStrength strength) override
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{
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NPNR_ASSERT(bel != BelId());
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int idx = get_bel_flat_index(bel);
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@ -511,7 +511,7 @@ struct Arch : BaseCtx
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refreshUiBel(bel);
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}
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void unbindBel(BelId bel)
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void unbindBel(BelId bel) override
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{
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NPNR_ASSERT(bel != BelId());
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int idx = get_bel_flat_index(bel);
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@ -522,7 +522,7 @@ struct Arch : BaseCtx
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refreshUiBel(bel);
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}
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Loc getBelLocation(BelId bel) const
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Loc getBelLocation(BelId bel) const override
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{
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Loc loc;
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loc.x = bel.location.x;
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@ -531,24 +531,24 @@ struct Arch : BaseCtx
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return loc;
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}
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BelId getBelByLocation(Loc loc) const;
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BelId getBelByLocation(Loc loc) const override;
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BelRange getBelsByTile(int x, int y) const;
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bool getBelGlobalBuf(BelId bel) const { return getBelType(bel) == id_DCCA; }
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bool getBelGlobalBuf(BelId bel) const override { return getBelType(bel) == id_DCCA; }
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bool checkBelAvail(BelId bel) const
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bool checkBelAvail(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[get_bel_flat_index(bel)] == nullptr;
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}
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CellInfo *getBoundBelCell(BelId bel) const
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CellInfo *getBoundBelCell(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[get_bel_flat_index(bel)];
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}
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CellInfo *getConflictingBelCell(BelId bel) const
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CellInfo *getConflictingBelCell(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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return bel_to_cell[get_bel_flat_index(bel)];
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@ -567,7 +567,7 @@ struct Arch : BaseCtx
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return range;
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}
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IdString getBelType(BelId bel) const
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IdString getBelType(BelId bel) const override
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{
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NPNR_ASSERT(bel != BelId());
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IdString id;
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@ -581,7 +581,7 @@ struct Arch : BaseCtx
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return ret;
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}
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WireId getBelPinWire(BelId bel, IdString pin) const;
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WireId getBelPinWire(BelId bel, IdString pin) const override;
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BelPinRange getWireBelPins(WireId wire) const
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{
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@ -598,9 +598,9 @@ struct Arch : BaseCtx
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// -------------------------------------------------
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WireId getWireByName(IdStringList name) const;
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WireId getWireByName(IdStringList name) const override;
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IdStringList getWireName(WireId wire) const
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IdStringList getWireName(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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std::array<IdString, 3> ids{x_ids.at(wire.location.x), y_ids.at(wire.location.y),
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@ -608,7 +608,7 @@ struct Arch : BaseCtx
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return IdStringList(ids);
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}
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IdString getWireType(WireId wire) const
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IdString getWireType(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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IdString id;
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@ -618,9 +618,9 @@ struct Arch : BaseCtx
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std::vector<std::pair<IdString, std::string>> getWireAttrs(WireId) const;
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uint32_t getWireChecksum(WireId wire) const { return wire.index; }
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uint32_t getWireChecksum(WireId wire) const override { return wire.index; }
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength)
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void bindWire(WireId wire, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire] == nullptr);
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@ -630,7 +630,7 @@ struct Arch : BaseCtx
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refreshUiWire(wire);
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}
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void unbindWire(WireId wire)
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void unbindWire(WireId wire) override
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{
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NPNR_ASSERT(wire != WireId());
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NPNR_ASSERT(wire_to_net[wire] != nullptr);
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@ -650,13 +650,13 @@ struct Arch : BaseCtx
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refreshUiWire(wire);
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}
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bool checkWireAvail(WireId wire) const
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bool checkWireAvail(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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return wire_to_net.find(wire) == wire_to_net.end() || wire_to_net.at(wire) == nullptr;
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}
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NetInfo *getBoundWireNet(WireId wire) const
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NetInfo *getBoundWireNet(WireId wire) const override
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{
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NPNR_ASSERT(wire != WireId());
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if (wire_to_net.find(wire) == wire_to_net.end())
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@ -665,18 +665,7 @@ struct Arch : BaseCtx
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return wire_to_net.at(wire);
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}
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WireId getConflictingWireWire(WireId wire) const { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const
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{
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NPNR_ASSERT(wire != WireId());
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if (wire_to_net.find(wire) == wire_to_net.end())
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return nullptr;
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else
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return wire_to_net.at(wire);
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}
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DelayInfo getWireDelay(WireId wire) const
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DelayInfo getWireDelay(WireId wire) const override
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{
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DelayInfo delay;
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delay.min_delay = 0;
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@ -714,10 +703,8 @@ struct Arch : BaseCtx
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// -------------------------------------------------
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PipId getPipByName(IdStringList name) const;
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IdStringList getPipName(PipId pip) const;
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IdString getPipType(PipId pip) const { return IdString(); }
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PipId getPipByName(IdStringList name) const override;
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IdStringList getPipName(PipId pip) const override;
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std::vector<std::pair<IdString, std::string>> getPipAttrs(PipId) const
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{
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@ -725,9 +712,9 @@ struct Arch : BaseCtx
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return ret;
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}
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uint32_t getPipChecksum(PipId pip) const { return pip.index; }
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uint32_t getPipChecksum(PipId pip) const override { return pip.index; }
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength)
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void bindPip(PipId pip, NetInfo *net, PlaceStrength strength) override
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip] == nullptr);
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@ -744,7 +731,7 @@ struct Arch : BaseCtx
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net->wires[dst].strength = strength;
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}
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void unbindPip(PipId pip)
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void unbindPip(PipId pip) override
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{
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip_to_net[pip] != nullptr);
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@ -760,13 +747,13 @@ struct Arch : BaseCtx
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pip_to_net[pip] = nullptr;
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}
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bool checkPipAvail(PipId pip) const
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bool checkPipAvail(PipId pip) const override
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{
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NPNR_ASSERT(pip != PipId());
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return pip_to_net.find(pip) == pip_to_net.end() || pip_to_net.at(pip) == nullptr;
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}
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NetInfo *getBoundPipNet(PipId pip) const
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NetInfo *getBoundPipNet(PipId pip) const override
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{
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NPNR_ASSERT(pip != PipId());
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if (pip_to_net.find(pip) == pip_to_net.end())
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@ -775,9 +762,7 @@ struct Arch : BaseCtx
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return pip_to_net.at(pip);
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}
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WireId getConflictingPipWire(PipId pip) const { return WireId(); }
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NetInfo *getConflictingPipNet(PipId pip) const
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NetInfo *getConflictingPipNet(PipId pip) const override
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{
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NPNR_ASSERT(pip != PipId());
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if (pip_to_net.find(pip) == pip_to_net.end())
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@ -799,7 +784,7 @@ struct Arch : BaseCtx
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return range;
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}
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WireId getPipSrcWire(PipId pip) const
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WireId getPipSrcWire(PipId pip) const override
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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@ -808,7 +793,7 @@ struct Arch : BaseCtx
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return wire;
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}
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WireId getPipDstWire(PipId pip) const
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WireId getPipDstWire(PipId pip) const override
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{
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WireId wire;
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NPNR_ASSERT(pip != PipId());
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@ -817,7 +802,7 @@ struct Arch : BaseCtx
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return wire;
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}
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DelayInfo getPipDelay(PipId pip) const
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DelayInfo getPipDelay(PipId pip) const override
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{
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DelayInfo delay;
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NPNR_ASSERT(pip != PipId());
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@ -871,7 +856,7 @@ struct Arch : BaseCtx
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return chip_info->tiletype_names[loc_info(pip)->pip_data[pip.index].tile_type].get();
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}
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Loc getPipLocation(PipId pip) const
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Loc getPipLocation(PipId pip) const override
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{
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Loc loc;
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loc.x = pip.location.x;
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@ -889,12 +874,12 @@ struct Arch : BaseCtx
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std::string get_pio_function_name(BelId bel) const;
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BelId get_pio_by_function_name(const std::string &name) const;
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PortType getBelPinType(BelId bel, IdString pin) const;
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PortType getBelPinType(BelId bel, IdString pin) const override;
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// -------------------------------------------------
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GroupId getGroupByName(IdStringList name) const;
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IdStringList getGroupName(GroupId group) const;
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GroupId getGroupByName(IdStringList name) const override;
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IdStringList getGroupName(GroupId group) const override;
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std::vector<GroupId> getGroups() const;
|
||||
std::vector<BelId> getGroupBels(GroupId group) const;
|
||||
std::vector<WireId> getGroupWires(GroupId group) const;
|
||||
@ -903,46 +888,46 @@ struct Arch : BaseCtx
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
delay_t estimateDelay(WireId src, WireId dst) const;
|
||||
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const;
|
||||
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
|
||||
delay_t getDelayEpsilon() const { return 20; }
|
||||
delay_t getRipupDelayPenalty() const;
|
||||
float getDelayNS(delay_t v) const { return v * 0.001; }
|
||||
DelayInfo getDelayFromNS(float ns) const
|
||||
delay_t estimateDelay(WireId src, WireId dst) const override;
|
||||
ArcBounds getRouteBoundingBox(WireId src, WireId dst) const override;
|
||||
delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const override;
|
||||
delay_t getDelayEpsilon() const override { return 20; }
|
||||
delay_t getRipupDelayPenalty() const override;
|
||||
float getDelayNS(delay_t v) const override { return v * 0.001; }
|
||||
DelayInfo getDelayFromNS(float ns) const override
|
||||
{
|
||||
DelayInfo del;
|
||||
del.min_delay = delay_t(ns * 1000);
|
||||
del.max_delay = delay_t(ns * 1000);
|
||||
return del;
|
||||
}
|
||||
uint32_t getDelayChecksum(delay_t v) const { return v; }
|
||||
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const;
|
||||
uint32_t getDelayChecksum(delay_t v) const override { return v; }
|
||||
bool getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay_t &budget) const override;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
bool pack();
|
||||
bool place();
|
||||
bool route();
|
||||
bool pack() override;
|
||||
bool place() override;
|
||||
bool route() override;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
std::vector<GraphicElement> getDecalGraphics(DecalId decal) const;
|
||||
|
||||
DecalXY getBelDecal(BelId bel) const;
|
||||
DecalXY getWireDecal(WireId wire) const;
|
||||
DecalXY getPipDecal(PipId pip) const;
|
||||
DecalXY getGroupDecal(GroupId group) const;
|
||||
DecalXY getBelDecal(BelId bel) const override;
|
||||
DecalXY getWireDecal(WireId wire) const override;
|
||||
DecalXY getPipDecal(PipId pip) const override;
|
||||
DecalXY getGroupDecal(GroupId group) const override;
|
||||
|
||||
// -------------------------------------------------
|
||||
|
||||
// Get the delay through a cell from one port to another, returning false
|
||||
// if no path exists
|
||||
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const;
|
||||
bool getCellDelay(const CellInfo *cell, IdString fromPort, IdString toPort, DelayInfo &delay) const override;
|
||||
// Get the port class, also setting clockInfoCount to the number of TimingClockingInfos associated with a port
|
||||
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const;
|
||||
TimingPortClass getPortTimingClass(const CellInfo *cell, IdString port, int &clockInfoCount) const override;
|
||||
// Get the TimingClockingInfo of a port
|
||||
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const;
|
||||
TimingClockingInfo getPortClockingInfo(const CellInfo *cell, IdString port, int index) const override;
|
||||
// Return true if a port is a net
|
||||
bool is_global_net(const NetInfo *net) const;
|
||||
|
||||
@ -952,29 +937,28 @@ struct Arch : BaseCtx
|
||||
|
||||
// -------------------------------------------------
|
||||
// Placement validity checks
|
||||
bool isValidBelForCellType(IdString cell_type, BelId bel) const { return cell_type == getBelType(bel); }
|
||||
|
||||
const std::vector<IdString> &getCellTypes() const { return cell_types; }
|
||||
|
||||
std::vector<BelBucketId> getBelBuckets() const { return buckets; }
|
||||
|
||||
IdString getBelBucketName(BelBucketId bucket) const { return bucket.name; }
|
||||
IdString getBelBucketName(BelBucketId bucket) const override { return bucket.name; }
|
||||
|
||||
BelBucketId getBelBucketByName(IdString name) const
|
||||
BelBucketId getBelBucketByName(IdString name) const override
|
||||
{
|
||||
BelBucketId bucket;
|
||||
bucket.name = name;
|
||||
return bucket;
|
||||
}
|
||||
|
||||
BelBucketId getBelBucketForBel(BelId bel) const
|
||||
BelBucketId getBelBucketForBel(BelId bel) const override
|
||||
{
|
||||
BelBucketId bucket;
|
||||
bucket.name = getBelType(bel);
|
||||
return bucket;
|
||||
}
|
||||
|
||||
BelBucketId getBelBucketForCellType(IdString cell_type) const
|
||||
BelBucketId getBelBucketForCellType(IdString cell_type) const override
|
||||
{
|
||||
BelBucketId bucket;
|
||||
bucket.name = cell_type;
|
||||
@ -992,13 +976,13 @@ struct Arch : BaseCtx
|
||||
return bels;
|
||||
}
|
||||
|
||||
bool isValidBelForCell(CellInfo *cell, BelId bel) const;
|
||||
bool isBelLocationValid(BelId bel) const;
|
||||
bool isValidBelForCell(CellInfo *cell, BelId bel) const override;
|
||||
bool isBelLocationValid(BelId bel) const override;
|
||||
|
||||
// Helper function for above
|
||||
bool slices_compatible(const std::vector<const CellInfo *> &cells) const;
|
||||
|
||||
void assignArchInfo();
|
||||
void assignArchInfo() override;
|
||||
|
||||
void permute_luts();
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user