diff --git a/ice40/arch.cc b/ice40/arch.cc
index 3803f842..93a49dde 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -141,18 +141,23 @@ Arch::Arch(ArchArgs args) : args(args)
 
 #ifdef ICE40_HX1K_ONLY
     if (args.type == ArchArgs::HX1K) {
+        fast_part = true;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
     } else {
         log_error("Unsupported iCE40 chip type.\n");
     }
 #else
     if (args.type == ArchArgs::LP384) {
+        fast_part = false;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_384));
     } else if (args.type == ArchArgs::LP1K || args.type == ArchArgs::HX1K) {
+        fast_part = args.type == ArchArgs::HX1K;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_1k));
     } else if (args.type == ArchArgs::UP5K) {
+        fast_part = false;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_5k));
     } else if (args.type == ArchArgs::LP8K || args.type == ArchArgs::HX8K) {
+        fast_part = args.type == ArchArgs::HX8K;
         chip_info = get_chip_info(reinterpret_cast<const RelPtr<ChipInfoPOD> *>(chipdb_blob_8k));
     } else {
         log_error("Unsupported iCE40 chip type.\n");
diff --git a/ice40/arch.h b/ice40/arch.h
index 51cbe725..0243e978 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -66,7 +66,8 @@ NPNR_PACKED_STRUCT(struct BelPortPOD {
 NPNR_PACKED_STRUCT(struct PipInfoPOD {
     // RelPtr<char> name;
     int32_t src, dst;
-    int32_t delay;
+    int32_t fast_delay;
+    int32_t slow_delay;
     int8_t x, y;
     int16_t src_seg, dst_seg;
     int16_t switch_mask;
@@ -89,6 +90,9 @@ NPNR_PACKED_STRUCT(struct WireInfoPOD {
     int32_t num_segments;
     RelPtr<WireSegmentPOD> segments;
 
+    int32_t fast_delay;
+    int32_t slow_delay;
+
     int8_t x, y;
     WireType type;
     int8_t padding_0;
@@ -344,6 +348,7 @@ struct ArchArgs
 
 struct Arch : BaseCtx
 {
+    bool fast_part;
     const ChipInfoPOD *chip_info;
     const PackageInfoPOD *package_info;
 
@@ -524,6 +529,11 @@ struct Arch : BaseCtx
     DelayInfo getWireDelay(WireId wire) const
     {
         DelayInfo delay;
+        NPNR_ASSERT(wire != WireId());
+        if (fast_part)
+            delay.delay =  chip_info->wire_data[wire.index].fast_delay;
+        else
+            delay.delay =  chip_info->wire_data[wire.index].slow_delay;
         return delay;
     }
 
@@ -637,7 +647,10 @@ struct Arch : BaseCtx
     {
         DelayInfo delay;
         NPNR_ASSERT(pip != PipId());
-        delay.delay = chip_info->pip_data[pip.index].delay;
+        if (fast_part)
+            delay.delay = chip_info->pip_data[pip.index].fast_delay;
+        else
+            delay.delay = chip_info->pip_data[pip.index].slow_delay;
         return delay;
     }
 
diff --git a/ice40/chipdb.py b/ice40/chipdb.py
index b6af8fcf..d020fedc 100644
--- a/ice40/chipdb.py
+++ b/ice40/chipdb.py
@@ -748,7 +748,8 @@ for wire in range(num_wires):
                 pi = dict()
                 pi["src"] = src
                 pi["dst"] = wire
-                pi["delay"] = pipdelay(src, wire)
+                pi["fast_delay"] = pipdelay(src, wire)
+                pi["slow_delay"] = pipdelay(src, wire)
                 pi["x"] = pip_xy[(src, wire)][0]
                 pi["y"] = pip_xy[(src, wire)][1]
                 pi["switch_mask"] = pip_xy[(src, wire)][2]
@@ -772,7 +773,8 @@ for wire in range(num_wires):
                 pi = dict()
                 pi["src"] = wire
                 pi["dst"] = dst
-                pi["delay"] = pipdelay(wire, dst)
+                pi["fast_delay"] = pipdelay(wire, dst)
+                pi["slow_delay"] = pipdelay(wire, dst)
                 pi["x"] = pip_xy[(wire, dst)][0]
                 pi["y"] = pip_xy[(wire, dst)][1]
                 pi["switch_mask"] = pip_xy[(wire, dst)][2]
@@ -891,6 +893,9 @@ for wire, info in enumerate(wireinfo):
     else:
         bba.u32(0, "segments")
 
+    bba.u32(0, "fast_delay")
+    bba.u32(0, "slow_delay")
+
     bba.u8(info["x"], "x")
     bba.u8(info["y"], "y")
     bba.u8(wiretypes[wire_type(info["name"])], "type")
@@ -923,7 +928,8 @@ for info in pipinfo:
     # bba.s("X%d/Y%d/%s->%s" % (info["x"], info["y"], src_segname, dst_segname), "name")
     bba.u32(info["src"], "src")
     bba.u32(info["dst"], "dst")
-    bba.u32(info["delay"], "delay")
+    bba.u32(info["fast_delay"], "fast_delay")
+    bba.u32(info["slow_delay"], "slow_delay")
     bba.u8(info["x"], "x")
     bba.u8(info["y"], "y")
     bba.u16(src_seg, "src_seg")