nexus: Add some infrastructure for DSP packing
Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah
parent
c7ad3cece6
commit
90608f2c89
@ -164,4 +164,26 @@ void rename_net(Context *ctx, NetInfo *net, IdString new_name)
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net->name = new_name;
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}
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std::vector<NetInfo *> create_bus(Context *ctx, IdString base_name, const std::string &postfix, int width)
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{
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std::vector<NetInfo *> nets;
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for (int i = 0; i < width; i++)
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nets.push_back(ctx->createNet(ctx->id(stringf("%s/%s[%d]", base_name.c_str(ctx), postfix.c_str(), i))));
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return nets;
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}
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void connect_bus(Context *ctx, CellInfo *cell, IdString port, std::vector<NetInfo *> &bus, PortType dir)
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{
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for (int i = 0; i < int(bus.size()); i++) {
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IdString p = ctx->id(stringf("%s%d", port.c_str(ctx), i));
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if (!cell->ports.count(p)) {
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cell->ports[p].name = p;
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cell->ports[p].type = dir;
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} else {
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NPNR_ASSERT(cell->ports.at(p).type == dir);
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}
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connect_port(ctx, bus.at(i), cell, p);
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}
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}
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NEXTPNR_NAMESPACE_END
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@ -104,6 +104,12 @@ void rename_port(Context *ctx, CellInfo *cell, IdString old_name, IdString new_n
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// Rename a net without invalidating pointers to it
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void rename_net(Context *ctx, NetInfo *net, IdString new_name);
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// Create a bus of nets
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std::vector<NetInfo *> create_bus(Context *ctx, IdString base_name, const std::string &postfix, int width);
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// Connect a bus of nets to a bus of ports
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void connect_bus(Context *ctx, CellInfo *cell, IdString port, std::vector<NetInfo *> &bus, PortType dir);
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void print_utilisation(const Context *ctx);
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NEXTPNR_NAMESPACE_END
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140
nexus/pack.cc
140
nexus/pack.cc
@ -264,11 +264,11 @@ struct NexusPacker
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std::unordered_map<IdString, BelId> reference_bels;
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void autocreate_ports(CellInfo *cell)
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void autocreate_ports(CellInfo *cell, bool include_outputs = false)
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{
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// Automatically create ports for all inputs of a cell; even if they were left off the instantiation
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// so we can tie them to constants as appropriate
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// This also checks for any cells that don't have corresponding bels
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// Automatically create ports for all inputs, and maybe outputs, of a cell; even if they were left off the
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// instantiation so we can tie them to constants as appropriate This also checks for any cells that don't have
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// corresponding bels
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if (!reference_bels.count(cell->type)) {
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// We need to look up a corresponding bel to get the list of input ports
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@ -288,7 +288,7 @@ struct NexusPacker
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BelId bel = reference_bels.at(cell->type);
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for (IdString pin : ctx->getBelPins(bel)) {
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PortType dir = ctx->getBelPinType(bel, pin);
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if (dir != PORT_IN)
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if (dir != PORT_IN && !include_outputs)
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continue;
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if (cell->ports.count(pin))
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continue;
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@ -1221,6 +1221,136 @@ struct NexusPacker
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}
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}
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// Function to check if a wire is general routing; and therefore skipped for cascade purposes
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bool is_general_routing(WireId wire)
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{
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std::string name = ctx->nameOf(ctx->wire_data(wire).name);
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if (name.size() == 3 && (name.substr(0, 2) == "JF" || name.substr(0, 2) == "JQ"))
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return false;
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if (name.size() == 12 && (name.substr(0, 10) == "JCIBMUXOUT"))
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return false;
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return true;
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}
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// Automatically generate cascade connections downstream of a cell
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// using the temporary placement that we use solely to access the routing graph
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void auto_cascade_cell(CellInfo *cell, BelId bel, const std::unordered_map<BelId, CellInfo *> &bel2cell)
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{
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for (auto port : sorted_ref(cell->ports)) {
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// Skip if not an output, or being used already for something else
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if (port.second.type != PORT_OUT || port.second.net != nullptr)
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continue;
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// Get the corresponding start wire
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WireId start_wire = ctx->getBelPinWire(bel, port.first);
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// Skip if the start wire doesn't actually exist
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if (start_wire == WireId())
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continue;
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// Standard BFS-type exploration
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std::queue<WireId> visit;
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visit.push(start_wire);
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int iter = 0;
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const int iter_limit = 1000;
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while (!visit.empty() && (iter++ < iter_limit)) {
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WireId cursor = visit.front();
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visit.pop();
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// Check for downstream bel pins
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bool found_active_pins = false;
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for (auto bp : ctx->getWireBelPins(cursor)) {
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auto fnd_cell = bel2cell.find(bp.bel);
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// Always skip unused bels, and don't set found_active_pins
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// so we can route through these if needed
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if (fnd_cell == bel2cell.end())
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continue;
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found_active_pins = true;
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// Skip outputs
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if (ctx->getBelPinType(bp.bel, bp.pin) != PORT_IN)
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continue;
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CellInfo *other_cell = fnd_cell->second;
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// Skip pins that are already in use
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if (get_net_or_empty(other_cell, bp.pin) != nullptr)
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continue;
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// Create the input if it doesn't exist
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if (!other_cell->ports.count(bp.pin))
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other_cell->addInput(bp.pin);
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// Make the connection
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connect_ports(ctx, cell, port.first, other_cell, bp.pin);
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}
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// By doing this we never attempt to route-through bels
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// that are actually in use
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if (found_active_pins)
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continue;
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// Search downstream pips for wires to add to the queue
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for (auto pip : ctx->getPipsDownhill(cursor))
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visit.push(ctx->getPipDstWire(pip));
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}
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}
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}
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// Insert all the cascade connections for a group of cells given the root
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void auto_cascade_group(CellInfo *root)
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{
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auto get_child_loc = [&](Loc base, const CellInfo *sub) {
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Loc l = base;
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l.x += sub->constr_x;
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l.y += sub->constr_y;
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l.z = sub->constr_abs_z ? sub->constr_z : (sub->constr_z + base.z);
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return l;
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};
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// We first create a temporary placement so we can access the routing graph
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bool found = false;
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std::unordered_map<BelId, CellInfo *> bel2cell;
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std::unordered_map<IdString, BelId> cell2bel;
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for (BelId root_bel : ctx->getBels()) {
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if (ctx->getBelType(root_bel) != root->type)
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continue;
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Loc root_loc = ctx->getBelLocation(root_bel);
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found = true;
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bel2cell.clear();
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cell2bel.clear();
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bel2cell[root_bel] = root;
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cell2bel[root->name] = root_bel;
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for (auto child : root->constr_children) {
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// Check that a valid placement exists for all children in the macro at this location
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Loc c_loc = get_child_loc(root_loc, child);
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BelId c_bel = ctx->getBelByLocation(c_loc);
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if (c_bel == BelId()) {
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found = false;
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break;
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}
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if (ctx->getBelType(c_bel) != child->type) {
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found = false;
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break;
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}
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bel2cell[c_bel] = child;
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cell2bel[child->name] = c_bel;
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}
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if (found)
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break;
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}
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if (!found)
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log_error("Failed to create temporary placement for cell '%s' of type '%s'\n", ctx->nameOf(root),
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ctx->nameOf(root->type));
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// Insert cascade connections from all cells in the macro
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auto_cascade_cell(root, cell2bel.at(root->name), bel2cell);
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for (auto child : root->constr_children)
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auto_cascade_cell(child, cell2bel.at(child->name), bel2cell);
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}
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explicit NexusPacker(Context *ctx) : ctx(ctx) {}
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void operator()()
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