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[interchange] Disallow site edges during general routing.

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This prevents the general router from routing through sites, which is
not legal in FPGA interchange.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-04-01 15:12:53 -07:00
parent 0d41fff3a7
commit 90aa1d3b7e
2 changed files with 23 additions and 5 deletions
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27
fpga_interchange/arch.cc
View File

@ -110,7 +110,7 @@ static std::string sha1_hash(const char *data, size_t size)
return buf.str();
}
Arch::Arch(ArchArgs args) : args(args)
Arch::Arch(ArchArgs args) : args(args), disallow_site_routing(false)
{
try {
blob_file.open(args.chipdb);
@ -870,6 +870,15 @@ bool Arch::route()
std::string router = str_or_default(settings, id("router"), defaultRouter);
// Disallow site routing during general routing. This is because
// "prepare_sites_for_routing" has already assigned routing for all sites
// in the design, and if the router wants to route-thru a site, it *MUST*
// use a pseudo-pip.
//
// It is not legal in the FPGA interchange to enter a site and not
// terminate at a BEL pin.
disallow_site_routing = true;
bool result;
if (router == "router1") {
result = router1(getCtx(), Router1Cfg(getCtx()));
@ -880,6 +889,8 @@ bool Arch::route()
log_error("FPGA interchange architecture does not support router '%s'\n", router.c_str());
}
disallow_site_routing = false;
getCtx()->attrs[getCtx()->id("step")] = std::string("route");
archInfoToAttributes();
@ -1717,10 +1728,6 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
}
if (pip_data.site != -1 && net != nullptr) {
// FIXME: This check isn't perfect. If a driver and sink are in the
// same site, it is possible for the router to route-thru the site
// ports without hitting a sink, which is not legal in the FPGA
// interchange.
NPNR_ASSERT(net->driver.cell != nullptr);
NPNR_ASSERT(net->driver.cell->bel != BelId());
@ -1746,6 +1753,16 @@ bool Arch::checkPipAvailForNet(PipId pip, NetInfo *net) const
}
}
if(disallow_site_routing && !valid_pip) {
// For now, if driver is not part of this site, and
// disallow_site_routing is set, disallow the edge.
return false;
}
// FIXME: This check isn't perfect. If a driver and sink are in the
// same site, it is possible for the router to route-thru the site
// ports without hitting a sink, which is not legal in the FPGA
// interchange.
if (!valid_pip) {
// See if one users can enter this site.
if (dst_wire_data.site == -1) {

1
fpga_interchange/arch.h
View File

@ -1081,6 +1081,7 @@ struct Arch : ArchAPI<ArchRanges>
Lookahead lookahead;
mutable RouteNodeStorage node_storage;
mutable SiteRoutingCache site_routing_cache;
bool disallow_site_routing;
CellParameters cell_parameters;
std::string chipdb_hash;