From 90ba958abe85ced03f16888644dd026b133cab36 Mon Sep 17 00:00:00 2001 From: Sergiusz Bazanski Date: Tue, 24 Jul 2018 03:03:31 +0100 Subject: [PATCH] ice40: fixes before review --- gui/fpgaviewwidget.cc | 3 +-- ice40/arch_place.cc | 1 + ice40/bitstream.cc | 12 ++++++------ ice40/cells.cc | 1 + ice40/pack.cc | 19 +++++-------------- ice40/pcf.cc | 25 ------------------------- 6 files changed, 14 insertions(+), 47 deletions(-) diff --git a/gui/fpgaviewwidget.cc b/gui/fpgaviewwidget.cc index cd042af5..e21af678 100644 --- a/gui/fpgaviewwidget.cc +++ b/gui/fpgaviewwidget.cc @@ -400,7 +400,6 @@ void FPGAViewWidget::paintGL() // Calculate world thickness to achieve a screen 1px/1.1px line. float thick1Px = mouseToWorldCoordinates(1, 0).x(); float thick11Px = mouseToWorldCoordinates(1.1, 0).x(); - float thick2Px = mouseToWorldCoordinates(2, 0).x(); // Draw grid. auto grid = LineShaderData(); @@ -419,7 +418,7 @@ void FPGAViewWidget::paintGL() for (int i = 0; i < 8; i++) lineShader_.draw(rendererData_->highlighted[i], colors_.highlight[i], thick11Px, matrix); - lineShader_.draw(rendererData_->selected, colors_.selected, thick2Px, matrix); + lineShader_.draw(rendererData_->selected, colors_.selected, thick11Px, matrix); rendererDataLock_.unlock(); } diff --git a/ice40/arch_place.cc b/ice40/arch_place.cc index 00c960b6..16cc757e 100644 --- a/ice40/arch_place.cc +++ b/ice40/arch_place.cc @@ -3,6 +3,7 @@ * * Copyright (C) 2018 Clifford Wolf * Copyright (C) 2018 David Shah + * Copyright (C) 2018 Serge Bazanski * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/ice40/bitstream.cc b/ice40/bitstream.cc index 7c3a26ca..e9851a83 100644 --- a/ice40/bitstream.cc +++ b/ice40/bitstream.cc @@ -87,7 +87,7 @@ void set_config(const TileInfoPOD &ti, std::vector> &tile_cf } // Set an IE_{EN,REN} logical bit in a tile config. Logical means enabled. -// On {HX,LP}1K devices these bits are active low, so we need to inver them. +// On {HX,LP}1K devices these bits are active low, so we need to invert them. void set_ie_bit_logical(const Context *ctx, const TileInfoPOD &ti, std::vector> &tile_cfg, const std::string &name, bool value) { @@ -101,9 +101,9 @@ void set_ie_bit_logical(const Context *ctx, const TileInfoPOD &ti, std::vectorparams.find(param); - if (found != cell->params.end()) { + if (found != cell->params.end()) return std::stoi(found->second); - } else + else return defval; } @@ -273,7 +273,7 @@ void write_asc(const Context *ctx, std::ostream &out) } std::unordered_set sb_io_used_by_pll; - std::unordered_set sb_io_used_by_user; + std::unordered_set sb_io_used_by_io; // Set logic cell config for (auto &cell : ctx->cells) { @@ -322,7 +322,7 @@ void write_asc(const Context *ctx, std::ostream &out) } else if (cell.second->type == ctx->id("SB_IO")) { const BelInfoPOD &beli = ci.bel_data[bel.index]; int x = beli.x, y = beli.y, z = beli.z; - sb_io_used_by_user.insert(Loc(x, y, z)); + sb_io_used_by_io.insert(Loc(x, y, z)); const TileInfoPOD &ti = bi.tiles_nonrouting[TILE_IO]; unsigned pin_type = get_param_or_def(cell.second.get(), ctx->id("PIN_TYPE")); bool neg_trigger = get_param_or_def(cell.second.get(), ctx->id("NEG_TRIGGER")); @@ -466,7 +466,7 @@ void write_asc(const Context *ctx, std::ostream &out) auto io_bel_loc = ctx->getBelLocation(io_bel); // Check that this SB_IO is either unused or just used as an output. - if (sb_io_used_by_user.count(io_bel_loc)) { + if (sb_io_used_by_io.count(io_bel_loc)) { log_error("SB_IO '%s' already in use, cannot route PLL through\n", ctx->getBelName(bel).c_str(ctx)); } sb_io_used_by_pll.insert(io_bel_loc); diff --git a/ice40/cells.cc b/ice40/cells.cc index 3215a38c..610bf85e 100644 --- a/ice40/cells.cc +++ b/ice40/cells.cc @@ -3,6 +3,7 @@ * * Copyright (C) 2018 Clifford Wolf * Copyright (C) 2018 David Shah + * Copyright (C) 2018 Serge Bazanski * * Permission to use, copy, modify, and/or distribute this software for any * purpose with or without fee is hereby granted, provided that the above diff --git a/ice40/pack.cc b/ice40/pack.cc index 8552e381..03b33190 100644 --- a/ice40/pack.cc +++ b/ice40/pack.cc @@ -736,22 +736,14 @@ static void pack_special(Context *ctx) new_cells.push_back(std::move(pt)); } - // Find wire driven by this port. - const auto &pll_beli = ctx->chip_info->bel_data[pll_bel.index]; - const WireInfoPOD *wirei = nullptr; - for (int i = 0; i < pll_beli.num_bel_wires; i++) { - auto bel_port = ctx->portPinToId(pll_beli.bel_wires[i].port); - if (port.name != bel_port) - continue; - wirei = &ctx->chip_info->wire_data[pll_beli.bel_wires[i].wire_index]; - break; - } - NPNR_ASSERT(wirei != nullptr); + // Find wire that will be driven by this port. + const auto pll_out_wire = ctx->getBelPinWire(pll_bel, ctx->portPinFromId(port.name)); + NPNR_ASSERT(pll_out_wire.index != -1); // Now, constrain all LUTs on the output of the signal to be at // the correct Bel relative to the PLL Bel. - int x = wirei->x; - int y = wirei->y; + int x = ctx->chip_info->wire_data[pll_out_wire.index].x; + int y = ctx->chip_info->wire_data[pll_out_wire.index].y; int z = 0; for (const auto &user : port.net->users) { NPNR_ASSERT(user.cell != nullptr); @@ -787,7 +779,6 @@ bool Arch::pack() log_break(); pack_constants(ctx); promote_globals(ctx); - pack_io(ctx); pack_lut_lutffs(ctx); pack_nonlut_ffs(ctx); diff --git a/ice40/pcf.cc b/ice40/pcf.cc index 3d0d0d84..ac1c8598 100644 --- a/ice40/pcf.cc +++ b/ice40/pcf.cc @@ -62,31 +62,6 @@ bool apply_pcf(Context *ctx, std::istream &in) log_info("constrained '%s' to bel '%s'\n", cell.c_str(), fnd_cell->second->attrs[ctx->id("BEL")].c_str()); } - } else if (cmd == "set_loc") { - size_t args_end = 1; - while (args_end < words.size() && words.at(args_end).at(0) == '-') - args_end++; - std::string cell = words.at(args_end); - std::string x = words.at(args_end + 1); - std::string y = words.at(args_end + 2); - std::string z = words.at(args_end + 3); - auto fnd_cell = ctx->cells.find(ctx->id(cell)); - if (fnd_cell == ctx->cells.end()) { - log_error("unmatched pcf constraint %s\n", cell.c_str()); - } - - Loc loc; - loc.x = std::stoi(x); - loc.y = std::stoi(y); - loc.z = std::stoi(z); - auto bel = ctx->getBelByLocation(loc); - if (bel == BelId()) { - log_error("constrain '%s': unknown bel\n", line.c_str()); - } - - fnd_cell->second->attrs[ctx->id("BEL")] = ctx->getBelName(bel).str(ctx); - log_info("constrained '%s' to bel '%s'\n", cell.c_str(), ctx->getBelName(bel).c_str(ctx)); - } else { log_error("unsupported pcf command '%s'\n", cmd.c_str()); }