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Add iCE40 blinky example

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Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
Clifford Wolf 2018-05-31 18:10:36 +02:00
parent 3b0d1beabb
commit 90c7e3b13d
3 changed files with 152 additions and 0 deletions
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module blinky (
input clk_pin,
output led1_pin,
output led2_pin,
output led3_pin,
output led4_pin,
output led5_pin
);
wire clk, led1, led2, led3, led4, led5;
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) led_iob [4:0] (
.PACKAGE_PIN({led1_pin, led2_pin, led3_pin, led4_pin, led5_pin}),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0({led1, led2, led3, led4, led5}),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) clk_iob (
.PACKAGE_PIN(clk_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(clk),
.D_IN_1()
);
localparam BITS = 5;
localparam LOG2DELAY = 22;
reg [BITS+LOG2DELAY-1:0] counter = 0;
reg [BITS-1:0] outcnt;
always @(posedge clk) begin
counter <= counter + 1;
outcnt <= counter >> LOG2DELAY;
end
assign {led1, led2, led3, led4, led5} = outcnt ^ (outcnt >> 1);
endmodule

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ice40/blinky.ys Normal file
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read_verilog blinky.v
read_verilog -lib +/ice40/cells_sim.v
synth -top blinky
abc -lut 4
techmap -map blinky_map.v
splitnets
opt_clean
stat
write_json blinky.json

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ice40/blinky_map.v Normal file
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module \$_DFF_P_ (input D, C, output Q);
ICESTORM_LC #(
.LUT_INIT(1),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(1),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(D),
.CLK(C),
.O(Q),
.I1(),
.I2(),
.I3(),
.CIN(),
.CEN(),
.SR(),
.LO(),
.COUT()
);
endmodule
module \$lut (A, Y);
parameter WIDTH = 0;
parameter LUT = 0;
input [WIDTH-1:0] A;
output Y;
generate
if (WIDTH == 1) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(), .I2(), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 2) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 3) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
if (WIDTH == 4) begin
ICESTORM_LC #(
.LUT_INIT(LUT),
.NEG_CLK(0),
.CARRY_ENABLE(0),
.DFF_ENABLE(0),
.SET_NORESET(0),
.ASYNC_SR(0)
) _TECHMAP_REPLACE_ (
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]), .O(Y),
.CLK(), .CIN(), .CEN(), .SR(), .LO(), .COUT()
);
end
endgenerate
endmodule