diff --git a/machxo2/arch_place.cc b/machxo2/arch_place.cc
index 9aab7b7f..6307fdb6 100644
--- a/machxo2/arch_place.cc
+++ b/machxo2/arch_place.cc
@@ -148,6 +148,7 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
             CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
             if (ff != nullptr) {
                 if (found_global_dpram) {
+                    // Do not allow SLICEC to have FF if there is already RAMW in it
                     if (i==4 || i==5) return false;
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
                     CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);