added a comment for constraining FF location
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@ -148,6 +148,7 @@ bool Arch::slices_compatible(LogicTileStatus *lts) const
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CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
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CellInfo *ff = lts->cells[(i << lc_idx_shift) | BEL_FF];
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if (ff != nullptr) {
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if (ff != nullptr) {
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if (found_global_dpram) {
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if (found_global_dpram) {
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// Do not allow SLICEC to have FF if there is already RAMW in it
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if (i==4 || i==5) return false;
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if (i==4 || i==5) return false;
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CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
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CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_CLKINV), global_clkinv);
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CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
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CHECK_EQUAL(bool(ff->ffInfo.flags & ArchCellInfo::FF_LSRINV), global_lsrinv);
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