Removed not tested/used code
This commit is contained in:
Miodrag Milanovic
myrtle
parent
0067bcc615
commit
91771895b6
213
machxo2/pack.cc
213
machxo2/pack.cc
@ -286,192 +286,6 @@ class MachXO2Packer
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return false;
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return false;
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}
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}
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// Pass to pack LUT5s into a newly created slice
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void pack_lut5xs()
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{
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log_info("Packing LUT5-7s...\n");
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// Gets the "COMB1" side of a LUT5, where we pack a LUT[67] into
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auto get_comb1_from_lut5 = [&](CellInfo *lut5) {
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NetInfo *f1 = lut5->getPort(id_F1);
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NPNR_ASSERT(f1 != nullptr);
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NPNR_ASSERT(f1->driver.cell != nullptr);
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return f1->driver.cell;
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};
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dict<IdString, std::pair<CellInfo *, CellInfo *>> lut5_roots, lut6_roots, lut7_roots;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (is_pfumx(ctx, ci)) {
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NetInfo *f0 = ci->ports.at(id_BLUT).net;
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if (f0 == nullptr)
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log_error("PFUMX '%s' has disconnected port 'BLUT'\n", ci->name.c_str(ctx));
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NetInfo *f1 = ci->ports.at(id_ALUT).net;
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if (f1 == nullptr)
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log_error("PFUMX '%s' has disconnected port 'ALUT'\n", ci->name.c_str(ctx));
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CellInfo *lut0 =
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(f0->driver.cell && f0->driver.cell->type == id_TRELLIS_COMB && f0->driver.port == id_F)
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? f0->driver.cell
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: nullptr;
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CellInfo *lut1 =
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(f1->driver.cell && f1->driver.cell->type == id_TRELLIS_COMB && f1->driver.port == id_F)
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? f1->driver.cell
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: nullptr;
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if (lut0 == nullptr || lut0->cluster != ClusterId())
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log_error("PFUMX '%s' has BLUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
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if (lut1 == nullptr || lut1->cluster != ClusterId())
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log_error("PFUMX '%s' has ALUT driven by cell other than a LUT\n", ci->name.c_str(ctx));
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lut0->addInput(id_F1);
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lut0->addInput(id_M);
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lut0->addOutput(id_OFX);
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ci->movePortTo(id_Z, lut0, id_OFX);
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ci->movePortTo(id_ALUT, lut0, id_F1);
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ci->movePortTo(id_C0, lut0, id_M);
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ci->disconnectPort(id_BLUT);
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lut5_roots[lut0->name] = {lut0, lut1};
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packed_cells.insert(ci->name);
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}
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}
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flush_cells();
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// Pack LUT6s
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (is_l6mux(ctx, ci)) {
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NetInfo *ofx0_0 = ci->ports.at(id_D0).net;
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if (ofx0_0 == nullptr)
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log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
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NetInfo *ofx0_1 = ci->ports.at(id_D1).net;
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if (ofx0_1 == nullptr)
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log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
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CellInfo *comb0 = (ofx0_0->driver.cell && ofx0_0->driver.cell->type == id_TRELLIS_COMB &&
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ofx0_0->driver.port == id_OFX)
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? ofx0_0->driver.cell
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: nullptr;
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CellInfo *comb1 = (ofx0_1->driver.cell && ofx0_1->driver.cell->type == id_TRELLIS_COMB &&
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ofx0_1->driver.port == id_OFX)
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? ofx0_1->driver.cell
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: nullptr;
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if (comb0 == nullptr) {
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if (!net_driven_by(ctx, ofx0_0, is_l6mux, id_Z))
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log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
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"('%s.%s')\n",
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ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
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ofx0_0->driver.port.c_str(ctx));
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continue;
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}
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if (lut6_roots.count(comb0->name))
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continue;
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if (comb1 == nullptr) {
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if (!net_driven_by(ctx, ofx0_1, is_l6mux, id_Z))
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log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX0 but not a LUT7 mux "
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"('%s.%s')\n",
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ci->name.c_str(ctx), ofx0_0->driver.cell->name.c_str(ctx),
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ofx0_0->driver.port.c_str(ctx));
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continue;
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}
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if (lut6_roots.count(comb1->name))
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continue;
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if (ctx->verbose)
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log_info(" mux '%s' forms part of a LUT6\n", cell.first.c_str(ctx));
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comb0 = get_comb1_from_lut5(comb0);
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comb1 = get_comb1_from_lut5(comb1);
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comb1->addInput(id_FXA);
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comb1->addInput(id_FXB);
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comb1->addInput(id_M);
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comb1->addOutput(id_OFX);
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ci->movePortTo(id_D0, comb1, id_FXA);
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ci->movePortTo(id_D1, comb1, id_FXB);
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ci->movePortTo(id_SD, comb1, id_M);
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ci->movePortTo(id_Z, comb1, id_OFX);
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lut6_roots[comb1->name] = {comb0, comb1};
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packed_cells.insert(ci->name);
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}
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}
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flush_cells();
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// Pack LUT7s
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (is_l6mux(ctx, ci)) {
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NetInfo *ofx1_0 = ci->ports.at(id_D0).net;
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if (ofx1_0 == nullptr)
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log_error("L6MUX21 '%s' has disconnected port 'D0'\n", ci->name.c_str(ctx));
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NetInfo *ofx1_1 = ci->ports.at(id_D1).net;
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if (ofx1_1 == nullptr)
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log_error("L6MUX21 '%s' has disconnected port 'D1'\n", ci->name.c_str(ctx));
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CellInfo *comb1 = (ofx1_0->driver.cell && ofx1_0->driver.cell->type == id_TRELLIS_COMB &&
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ofx1_0->driver.port == id_OFX)
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? ofx1_0->driver.cell
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: nullptr;
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CellInfo *comb3 = (ofx1_1->driver.cell && ofx1_1->driver.cell->type == id_TRELLIS_COMB &&
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ofx1_1->driver.port == id_OFX)
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? ofx1_1->driver.cell
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: nullptr;
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if (comb1 == nullptr)
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log_error("L6MUX21 '%s' has D0 driven by cell other than a SLICE OFX ('%s.%s')\n",
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ci->name.c_str(ctx), ofx1_0->driver.cell->name.c_str(ctx),
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ofx1_0->driver.port.c_str(ctx));
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if (comb3 == nullptr)
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log_error("L6MUX21 '%s' has D1 driven by cell other than a SLICE OFX ('%s.%s')\n",
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ci->name.c_str(ctx), ofx1_1->driver.cell->name.c_str(ctx),
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ofx1_1->driver.port.c_str(ctx));
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NetInfo *fxa_0 = comb1->ports.at(id_FXA).net;
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if (fxa_0 == nullptr)
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log_error("SLICE '%s' has disconnected port 'FXA'\n", comb1->name.c_str(ctx));
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NetInfo *fxa_1 = comb3->ports.at(id_FXA).net;
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if (fxa_1 == nullptr)
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log_error("SLICE '%s' has disconnected port 'FXA'\n", comb3->name.c_str(ctx));
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CellInfo *comb2 = net_driven_by(
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ctx, fxa_1,
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[](const Context *ctx, const CellInfo *ci) {
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(void)ctx;
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return ci->type == id_TRELLIS_COMB;
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},
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id_OFX);
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if (comb2 == nullptr)
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log_error("SLICE '%s' has FXA driven by cell other than a SLICE OFX0 ('%s.%s')\n",
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comb3->name.c_str(ctx), fxa_1->driver.cell->name.c_str(ctx),
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fxa_1->driver.port.c_str(ctx));
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comb2 = get_comb1_from_lut5(comb2);
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comb2->addInput(id_FXA);
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comb2->addInput(id_FXB);
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comb2->addInput(id_M);
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comb2->addOutput(id_OFX);
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ci->movePortTo(id_D0, comb2, id_FXA);
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ci->movePortTo(id_D1, comb2, id_FXB);
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ci->movePortTo(id_SD, comb2, id_M);
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ci->movePortTo(id_Z, comb2, id_OFX);
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lut7_roots[comb2->name] = {comb1, comb3};
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packed_cells.insert(ci->name);
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}
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}
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for (auto &root : lut7_roots) {
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auto &cells = root.second;
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cells.second->cluster = cells.second->name;
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cells.second->constr_abs_z = true;
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cells.second->constr_z = (1 << Arch::lc_idx_shift) | Arch::BEL_COMB;
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rel_constr_cells(cells.second, cells.first, (4 << Arch::lc_idx_shift));
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}
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for (auto &root : lut6_roots) {
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auto &cells = root.second;
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rel_constr_cells(cells.second, cells.first, (2 << Arch::lc_idx_shift));
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}
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for (auto &root : lut5_roots) {
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auto &cells = root.second;
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rel_constr_cells(cells.first, cells.second, (1 << Arch::lc_idx_shift));
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}
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flush_cells();
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}
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// Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
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// Simple "packer" to remove nextpnr IOBUFs, this assumes IOBUFs are manually instantiated
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void pack_io()
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void pack_io()
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{
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{
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@ -1222,32 +1036,6 @@ class MachXO2Packer
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new_cells.push_back(std::move(zero_cell));
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new_cells.push_back(std::move(zero_cell));
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}
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}
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int lookup_delay(const std::string &del_mode)
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{
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if (del_mode == "USER_DEFINED")
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return 0;
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else if (del_mode == "DQS_ALIGNED_X2")
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return 6;
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else if (del_mode == "DQS_CMD_CLK")
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return 9;
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else if (del_mode == "ECLK_ALIGNED")
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return 21;
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else if (del_mode == "ECLK_CENTERED")
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return 11;
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else if (del_mode == "ECLKBRIDGE_ALIGNED")
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return 39;
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else if (del_mode == "ECLKBRIDGE_CENTERED")
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return 29;
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else if (del_mode == "SCLK_ALIGNED")
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return 50;
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else if (del_mode == "SCLK_CENTERED")
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return 39;
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else if (del_mode == "SCLK_ZEROHOLD")
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return 59;
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else
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log_error("Unsupported DEL_MODE '%s'\n", del_mode.c_str());
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}
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void generate_constraints()
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void generate_constraints()
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{
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{
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log_info("Generating derived timing constraints...\n");
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log_info("Generating derived timing constraints...\n");
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@ -1460,7 +1248,6 @@ class MachXO2Packer
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pack_dram();
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pack_dram();
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pack_carries();
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pack_carries();
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pack_luts();
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pack_luts();
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pack_lut5xs();
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pack_ffs();
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pack_ffs();
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generate_constraints();
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generate_constraints();
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ctx->fixupHierarchy();
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ctx->fixupHierarchy();
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