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mistral: Fix ENA and ACLR bitstream generation

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-15 10:26:27 +01:00
parent 4d32c4f2fc
commit 9221acc9e2
4 changed files with 11 additions and 4 deletions
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1
mistral/arch.h
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@ -65,6 +65,7 @@ struct LABInfo
std::array<WireId, 2> aclr_wires; std::array<WireId, 2> aclr_wires;
WireId sclr_wire, sload_wire; WireId sclr_wire, sload_wire;
// TODO: LAB configuration (control set etc) // TODO: LAB configuration (control set etc)
std::array<bool, 2> aclr_used;
}; };
struct PinInfo struct PinInfo

4
mistral/bitstream.cc
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@ -283,7 +283,7 @@ struct MistralBitgen
if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to
// ensure different constants don't collide // ensure different constants don't collide
cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, true); cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, true);
cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, !ff->ffInfo.ctrlset.ena.inverted); cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted);
} else { } else {
cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, false); cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, false);
} }
@ -315,7 +315,7 @@ struct MistralBitgen
const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL}; const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL};
for (int i = 0; i < 2; i++) { for (int i = 0; i < 2; i++) {
// Quartus seems to set unused ACLRs to CLKI2... // Quartus seems to set unused ACLRs to CLKI2...
if (ctx->getBoundWireNet(lab_data.aclr_wires[i]) == nullptr) if (!lab_data.aclr_used[i])
cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, CycloneV::CLKI2); cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, CycloneV::CLKI2);
else else
cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1); cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1);

4
mistral/globals.cc
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@ -26,8 +26,8 @@ NEXTPNR_NAMESPACE_BEGIN
void Arch::create_clkbuf(int x, int y) void Arch::create_clkbuf(int x, int y)
{ {
for (int z = 0; z < 4; z++) { for (int z = 0; z < 4; z++) {
if (z != 2) if (z != 2)
continue; // TODO: why do other Zs not work? continue; // TODO: why do other Zs not work?
// For now we only consider the input path from general routing, other inputs like dedicated clock pins are // For now we only consider the input path from general routing, other inputs like dedicated clock pins are
// still a TODO // still a TODO
BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA); BelId bel = add_bel(x, y, id(stringf("CLKBUF[%d]", z)), id_MISTRAL_CLKENA);

6
mistral/lab.cc
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@ -616,6 +616,11 @@ void Arch::assign_control_sets(uint32_t lab)
bool legal = worker.run(this, lab); bool legal = worker.run(this, lab);
NPNR_ASSERT(legal); NPNR_ASSERT(legal);
auto &lab_data = labs.at(lab); auto &lab_data = labs.at(lab);
for (int j = 0; j < 2; j++) {
lab_data.aclr_used[j] = false;
}
for (uint8_t alm = 0; alm < 10; alm++) { for (uint8_t alm = 0; alm < 10; alm++) {
auto &alm_data = lab_data.alms.at(alm); auto &alm_data = lab_data.alms.at(alm);
for (uint8_t i = 0; i < 4; i++) { for (uint8_t i = 0; i < 4; i++) {
@ -648,6 +653,7 @@ void Arch::assign_control_sets(uint32_t lab)
log_info("Assigned ACLR set %d to FF %s (%s)\n", i, nameOf(ff), getCtx()->nameOfBel(ff_bel)); log_info("Assigned ACLR set %d to FF %s (%s)\n", i, nameOf(ff), getCtx()->nameOfBel(ff_bel));
} }
reserve_route(lab_data.aclr_wires[j], aclr_wire); reserve_route(lab_data.aclr_wires[j], aclr_wire);
lab_data.aclr_used[j] = (aclr_sig.net != nullptr);
alm_data.aclr_idx[i / 2] = j; alm_data.aclr_idx[i / 2] = j;
break; break;
} }