mistral: Fix ENA and ACLR bitstream generation
Signed-off-by: gatecat <gatecat@ds0.me>
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@ -65,6 +65,7 @@ struct LABInfo
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std::array<WireId, 2> aclr_wires;
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WireId sclr_wire, sload_wire;
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// TODO: LAB configuration (control set etc)
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std::array<bool, 2> aclr_used;
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};
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struct PinInfo
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@ -283,7 +283,7 @@ struct MistralBitgen
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if (get_net_or_empty(ff, id_ENA) != nullptr) { // not using ffInfo.ctrlset, this has a fake net always to
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// ensure different constants don't collide
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cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, true);
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cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, !ff->ffInfo.ctrlset.ena.inverted);
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cv->bmux_b_set(CycloneV::LAB, pos, en_ninv[ce_idx], 0, ff->ffInfo.ctrlset.ena.inverted);
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} else {
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cv->bmux_b_set(CycloneV::LAB, pos, en_en[ce_idx], 0, false);
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}
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@ -315,7 +315,7 @@ struct MistralBitgen
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const std::array<CycloneV::bmux_type_t, 2> aclr_inp{CycloneV::ACLR0_SEL, CycloneV::ACLR1_SEL};
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for (int i = 0; i < 2; i++) {
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// Quartus seems to set unused ACLRs to CLKI2...
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if (ctx->getBoundWireNet(lab_data.aclr_wires[i]) == nullptr)
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if (!lab_data.aclr_used[i])
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cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, CycloneV::CLKI2);
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else
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cv->bmux_m_set(CycloneV::LAB, pos, aclr_inp[i], 0, (i == 1) ? CycloneV::GIN0 : CycloneV::GIN1);
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@ -616,6 +616,11 @@ void Arch::assign_control_sets(uint32_t lab)
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bool legal = worker.run(this, lab);
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NPNR_ASSERT(legal);
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auto &lab_data = labs.at(lab);
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for (int j = 0; j < 2; j++) {
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lab_data.aclr_used[j] = false;
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}
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for (uint8_t alm = 0; alm < 10; alm++) {
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auto &alm_data = lab_data.alms.at(alm);
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for (uint8_t i = 0; i < 4; i++) {
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@ -648,6 +653,7 @@ void Arch::assign_control_sets(uint32_t lab)
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log_info("Assigned ACLR set %d to FF %s (%s)\n", i, nameOf(ff), getCtx()->nameOfBel(ff_bel));
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}
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reserve_route(lab_data.aclr_wires[j], aclr_wire);
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lab_data.aclr_used[j] = (aclr_sig.net != nullptr);
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alm_data.aclr_idx[i / 2] = j;
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break;
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}
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