Unfurl comments for clangformat

This commit is contained in:
Eddie Hung 2018-08-08 08:01:24 -07:00
parent d21e5a4b10
commit 936b52eafc

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@ -60,14 +60,11 @@ struct Timing
{ {
const auto clk_period = delay_t(1.0e12 / ctx->target_freq); const auto clk_period = delay_t(1.0e12 / ctx->target_freq);
// First, compute the topographical order of nets to walk through // First, compute the topographical order of nets to walk through the circuit, assuming it is a _acyclic_ graph
// the circuit, assuming it is a _acyclic_ graph // TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial loops
// TODO(eddieh): Handle the case where it is cyclic, e.g. combinatorial
// loops
std::vector<NetInfo *> topographical_order; std::vector<NetInfo *> topographical_order;
std::unordered_map<const NetInfo *, TimingData> net_data; std::unordered_map<const NetInfo *, TimingData> net_data;
// In lieu of deleting edges from the graph, simply count // In lieu of deleting edges from the graph, simply count the number of fanins to each output port
// the number of fanins to each output port
std::unordered_map<const PortInfo *, unsigned> port_fanin; std::unordered_map<const PortInfo *, unsigned> port_fanin;
std::vector<IdString> input_ports; std::vector<IdString> input_ports;
@ -87,8 +84,7 @@ struct Timing
for (auto o : output_ports) { for (auto o : output_ports) {
IdString clockPort; IdString clockPort;
TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clockPort); TimingPortClass portClass = ctx->getPortTimingClass(cell.second.get(), o->name, clockPort);
// If output port is influenced by a clock (e.g. FF output) // If output port is influenced by a clock (e.g. FF output) then add it to the ordering as a timing start-point
// then add it to the ordering as a timing start-point
if (portClass == TMG_REGISTER_OUTPUT) { if (portClass == TMG_REGISTER_OUTPUT) {
DelayInfo clkToQ; DelayInfo clkToQ;
ctx->getCellDelay(cell.second.get(), clockPort, o->name, clkToQ); ctx->getCellDelay(cell.second.get(), clockPort, o->name, clkToQ);
@ -100,9 +96,7 @@ struct Timing
topographical_order.emplace_back(o->net); topographical_order.emplace_back(o->net);
net_data.emplace(o->net, TimingData{}); net_data.emplace(o->net, TimingData{});
} }
// Otherwise, for all driven input ports on this cell, // Otherwise, for all driven input ports on this cell, if a timing arc exists between the input and the current output port, increment fanin counter
// if a timing arc exists between the input and
// the current output port, increment fanin counter
for (auto i : input_ports) { for (auto i : input_ports) {
DelayInfo comb_delay; DelayInfo comb_delay;
bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay); bool is_path = ctx->getCellDelay(cell.second.get(), i, o->name, comb_delay);
@ -127,9 +121,7 @@ struct Timing
std::deque<NetInfo *> queue(topographical_order.begin(), topographical_order.end()); std::deque<NetInfo *> queue(topographical_order.begin(), topographical_order.end());
// Now walk the design, from the start points identified previously, // Now walk the design, from the start points identified previously, building up a topographical order
// building
// up a topographical order
while (!queue.empty()) { while (!queue.empty()) {
const auto net = queue.front(); const auto net = queue.front();
queue.pop_front(); queue.pop_front();
@ -153,8 +145,7 @@ struct Timing
bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay); bool is_path = ctx->getCellDelay(usr.cell, usr.port, port.first, comb_delay);
if (!is_path) if (!is_path)
continue; continue;
// Decrement the fanin count, and only add to topographical // Decrement the fanin count, and only add to topographical order if all its fanins have already been visited
// order if all its fanins have already been visited
auto it = port_fanin.find(&port.second); auto it = port_fanin.find(&port.second);
NPNR_ASSERT(it != port_fanin.end()); NPNR_ASSERT(it != port_fanin.end());
if (--it->second == 0) { if (--it->second == 0) {
@ -166,12 +157,10 @@ struct Timing
} }
} }
// Sanity check to ensure that all ports where fanins were recorded // Sanity check to ensure that all ports where fanins were recorded were indeed visited
// were indeed visited
NPNR_ASSERT(port_fanin.empty()); NPNR_ASSERT(port_fanin.empty());
// Go forwards topographically to find the maximum arrival time // Go forwards topographically to find the maximum arrival time and max path length for each net
// and max path length for each net
for (auto net : topographical_order) { for (auto net : topographical_order) {
auto &nd = net_data.at(net); auto &nd = net_data.at(net);
const auto net_arrival = nd.max_arrival; const auto net_arrival = nd.max_arrival;
@ -197,9 +186,7 @@ struct Timing
auto &data = net_data[port.second.net]; auto &data = net_data[port.second.net];
auto &arrival = data.max_arrival; auto &arrival = data.max_arrival;
arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay()); arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
if (!budget_override) { // Do not increment path length if if (!budget_override) { // Do not increment path length if budget overriden since it doesn't require a share of the slack
// budget overriden
// since it doesn't require a share of the slack
auto &path_length = data.max_path_length; auto &path_length = data.max_path_length;
path_length = std::max(path_length, net_length_plus_one); path_length = std::max(path_length, net_length_plus_one);
} }
@ -210,8 +197,7 @@ struct Timing
const NetInfo *crit_net = nullptr; const NetInfo *crit_net = nullptr;
// Now go backwards topographically to determine the minimum path slack, // Now go backwards topographically to determine the minimum path slack, and to distribute all path slack evenly between all nets on the path
// and to distribute all path slack evenly between all nets on the path
for (auto net : boost::adaptors::reverse(topographical_order)) { for (auto net : boost::adaptors::reverse(topographical_order)) {
auto &nd = net_data.at(net); auto &nd = net_data.at(net);
const delay_t net_length_plus_one = nd.max_path_length + 1; const delay_t net_length_plus_one = nd.max_path_length + 1;
@ -348,9 +334,7 @@ void assign_budget(Context *ctx, bool quiet)
} }
} }
// For slack redistribution, if user has not specified a frequency // For slack redistribution, if user has not specified a frequency dynamically adjust the target frequency to be the currently achieved maximum
// dynamically adjust the target frequency to be the currently
// achieved maximum
if (ctx->auto_freq && ctx->slack_redist_iter > 0) { if (ctx->auto_freq && ctx->slack_redist_iter > 0) {
delay_t default_slack = delay_t(1.0e12 / ctx->target_freq); delay_t default_slack = delay_t(1.0e12 / ctx->target_freq);
ctx->target_freq = 1e12 / (default_slack - timing.min_slack); ctx->target_freq = 1e12 / (default_slack - timing.min_slack);