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refactor: Replace getXName().c_str(ctx) with ctx->nameOfX

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This makes the ongoing migration to IdStringList easier.

Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
D. Shah 2021-01-29 12:58:41 +00:00
parent 6d23461bcd
commit 9388df19d3
9 changed files with 34 additions and 39 deletions
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8
common/archcheck.cc
View File

@ -48,7 +48,7 @@ void archcheck_names(const Context *ctx)
IdString name = ctx->getWireName(wire);
WireId wire2 = ctx->getWireByName(name);
if (wire != wire2) {
log_error("wire != wire2, name = %s\n", name.c_str(ctx));
log_error("wire != wire2, name = %s\n", ctx->nameOfWire(wire));
}
}
@ -67,7 +67,7 @@ void archcheck_names(const Context *ctx)
IdString name = ctx->getPipName(pip);
PipId pip2 = ctx->getPipByName(name);
if (pip != pip2) {
log_error("pip != pip2, name = %s\n", name.c_str(ctx));
log_error("pip != pip2, name = %s\n", ctx->nameOfPip(pip));
}
}
#endif
@ -109,7 +109,7 @@ void archcheck_locs(const Context *ctx)
if (bel == BelId())
continue;
Loc loc = ctx->getBelLocation(bel);
dbg(" + %d %s\n", z, ctx->getBelName(bel).c_str(ctx));
dbg(" + %d %s\n", z, ctx->nameOfBel(bel));
log_assert(x == loc.x);
log_assert(y == loc.y);
log_assert(z == loc.z);
@ -118,7 +118,7 @@ void archcheck_locs(const Context *ctx)
for (BelId bel : ctx->getBelsByTile(x, y)) {
Loc loc = ctx->getBelLocation(bel);
dbg(" - %d %s\n", loc.z, ctx->getBelName(bel).c_str(ctx));
dbg(" - %d %s\n", loc.z, ctx->nameOfBel(bel));
log_assert(x == loc.x);
log_assert(y == loc.y);
log_assert(usedz.count(loc.z));

6
common/placer1.cc
View File

@ -563,9 +563,9 @@ class SAPlacer
}
commit_cost_changes(moveChange);
#if 0
log_info("swap %s -> %s\n", cell->name.c_str(ctx), ctx->getBelName(newBel).c_str(ctx));
log_info("swap %s -> %s\n", cell->name.c_str(ctx), ctx->nameOfBel(newBel));
if (other_cell != nullptr)
log_info("swap %s -> %s\n", other_cell->name.c_str(ctx), ctx->getBelName(oldBel).c_str(ctx));
log_info("swap %s -> %s\n", other_cell->name.c_str(ctx), ctx->nameOfBel(oldBel));
#endif
return true;
swap_fail:
@ -590,7 +590,7 @@ class SAPlacer
{
BelId oldBel = cell->bel;
#if 0
log_info("%s old: %s new: %s\n", cell->name.c_str(ctx), ctx->getBelName(cell->bel).c_str(ctx), ctx->getBelName(newBel).c_str(ctx));
log_info("%s old: %s new: %s\n", cell->name.c_str(ctx), ctx->nameOfBel(cell->bel), ctx->nameOfBel(newBel));
#endif
CellInfo *bound = ctx->getBoundBelCell(newBel);
if (bound != nullptr)

3
common/timing.cc
View File

@ -885,8 +885,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
auto pip = it->second.pip;
NPNR_ASSERT(pip != PipId());
delay = ctx->getPipDelay(pip).maxDelay();
log_info(" %1.3f %s\n", ctx->getDelayNS(delay),
ctx->getPipName(pip).c_str(ctx));
log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
cursor = ctx->getPipSrcWire(pip);
}
}

13
ecp5/globals.cc
View File

@ -238,8 +238,7 @@ class Ecp5GlobalRouter
if (visit.empty() || visit.size() > 50000) {
if (allow_fail)
return false;
log_error("cannot route global from %s to %s.\n", ctx->getWireName(src).c_str(ctx),
ctx->getWireName(dst).c_str(ctx));
log_error("cannot route global from %s to %s.\n", ctx->nameOfWire(src), ctx->nameOfWire(dst));
}
cursor = visit.front();
visit.pop();
@ -325,8 +324,8 @@ class Ecp5GlobalRouter
} else {
// Check for dedicated routing
if (has_short_route(ctx->getBelPinWire(drv_bel, drv.port), ctx->getBelPinWire(dcc->bel, id_CLKI))) {
// log_info("dedicated route %s -> %s\n", ctx->getWireName(ctx->getBelPinWire(drv_bel,
// drv.port)).c_str(ctx), ctx->getBelName(dcc->bel).c_str(ctx));
// log_info("dedicated route %s -> %s\n", ctx->nameOfWire(ctx->getBelPinWire(drv_bel,
// drv.port)), ctx->nameOfWire(dcc->bel));
dedicated_routing = true;
return 0;
}
@ -347,8 +346,8 @@ class Ecp5GlobalRouter
while (true) {
if (visit.empty() || visit.size() > 10000) {
// log_info ("dist %s -> %s = inf\n", ctx->getWireName(src).c_str(ctx),
// ctx->getWireName(dst).c_str(ctx));
// log_info ("dist %s -> %s = inf\n", ctx->nameOfWire(src),
// ctx->nameOfWire(dst));
return false;
}
cursor = visit.front();
@ -372,7 +371,7 @@ class Ecp5GlobalRouter
cursor = ctx->getPipSrcWire(fnd->second);
length++;
}
// log_info ("dist %s -> %s = %d\n", ctx->getWireName(src).c_str(ctx), ctx->getWireName(dst).c_str(ctx),
// log_info ("dist %s -> %s = %d\n", ctx->nameOfWire(src), ctx->nameOfWire(dst),
// length);
return length < thresh;
}

2
ecp5/pack.cc
View File

@ -1853,7 +1853,7 @@ class Ecp5Packer
next = upstream.front();
upstream.pop();
if (ctx->debug)
log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx));
log_info(" visited %s\n", ctx->nameOfWire(next));
IdString basename = ctx->getWireBasename(next);
if (basename == bnke_name || basename == global_name) {
break;

22
gui/designwidget.cc
View File

@ -631,7 +631,7 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
addProperty(portInfoItem, QVariant::String, "Name", item.c_str(ctx));
addProperty(portInfoItem, QVariant::Int, "Type", int(ctx->getBelPinType(bel, item)));
WireId wire = ctx->getBelPinWire(bel, item);
addProperty(portInfoItem, QVariant::String, "Wire", ctx->getWireName(wire).c_str(ctx), ElementType::WIRE);
addProperty(portInfoItem, QVariant::String, "Wire", ctx->nameOfWire(wire), ElementType::WIRE);
}
} else if (type == ElementType::WIRE) {
std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
@ -644,8 +644,8 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
addProperty(topItem, QVariant::String, "Type", ctx->getWireType(wire).c_str(ctx));
addProperty(topItem, QVariant::Bool, "Available", ctx->checkWireAvail(wire));
addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundWireNet(wire)), ElementType::NET);
addProperty(topItem, QVariant::String, "Conflicting Wire",
ctx->getWireName(ctx->getConflictingWireWire(wire)).c_str(ctx), ElementType::WIRE);
addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingWireWire(wire)),
ElementType::WIRE);
addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingWireNet(wire)),
ElementType::NET);
@ -666,7 +666,7 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
for (const auto &item : ctx->getWireBelPins(wire)) {
QString belname = "";
if (item.bel != BelId())
belname = ctx->getBelName(item.bel).c_str(ctx);
belname = ctx->nameOfBel(item.bel);
QString pinname = item.pin.c_str(ctx);
QtProperty *dhItem = addSubGroup(belpinsItem, belname + "-" + pinname);
@ -707,16 +707,15 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
if (ctx->getConflictingPipWire(pip) != WireId()) {
addProperty(topItem, QVariant::String, "Conflicting Wire",
ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingPipWire(pip)),
ElementType::WIRE);
} else {
addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
}
addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
ElementType::NET);
addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),
ElementType::WIRE);
addProperty(topItem, QVariant::String, "Dest Wire", ctx->getWireName(ctx->getPipDstWire(pip)).c_str(ctx),
addProperty(topItem, QVariant::String, "Src Wire", ctx->nameOfWire(ctx->getPipSrcWire(pip)), ElementType::WIRE);
addProperty(topItem, QVariant::String, "Dest Wire", ctx->nameOfWire(ctx->getPipDstWire(pip)),
ElementType::WIRE);
QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
@ -769,14 +768,13 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
QtProperty *wiresItem = addSubGroup(topItem, "Wires");
for (auto &item : net->wires) {
auto name = ctx->getWireName(item.first).c_str(ctx);
auto name = ctx->nameOfWire(item.first);
QtProperty *wireItem = addSubGroup(wiresItem, name);
addProperty(wireItem, QVariant::String, "Wire", name, ElementType::WIRE);
if (item.second.pip != PipId())
addProperty(wireItem, QVariant::String, "Pip", ctx->getPipName(item.second.pip).c_str(ctx),
ElementType::PIP);
addProperty(wireItem, QVariant::String, "Pip", ctx->nameOfPip(item.second.pip), ElementType::PIP);
else
addProperty(wireItem, QVariant::String, "Pip", "", ElementType::PIP);

8
gui/fpgaviewwidget.cc
View File

@ -779,22 +779,22 @@ void FPGAViewWidget::mouseMoveEvent(QMouseEvent *event)
rendererArgs_->x = event->x();
rendererArgs_->y = event->y();
if (closest.type == ElementType::BEL) {
rendererArgs_->hintText = std::string("BEL\n") + ctx_->getBelName(closest.bel).c_str(ctx_);
rendererArgs_->hintText = std::string("BEL\n") + ctx_->getBelName(closest.bel).str(ctx_);
CellInfo *cell = ctx_->getBoundBelCell(closest.bel);
if (cell != nullptr)
rendererArgs_->hintText += std::string("\nCELL\n") + ctx_->nameOf(cell);
} else if (closest.type == ElementType::WIRE) {
rendererArgs_->hintText = std::string("WIRE\n") + ctx_->getWireName(closest.wire).c_str(ctx_);
rendererArgs_->hintText = std::string("WIRE\n") + ctx_->getWireName(closest.wire).str(ctx_);
NetInfo *net = ctx_->getBoundWireNet(closest.wire);
if (net != nullptr)
rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
} else if (closest.type == ElementType::PIP) {
rendererArgs_->hintText = std::string("PIP\n") + ctx_->getPipName(closest.pip).c_str(ctx_);
rendererArgs_->hintText = std::string("PIP\n") + ctx_->getPipName(closest.pip).str(ctx_);
NetInfo *net = ctx_->getBoundPipNet(closest.pip);
if (net != nullptr)
rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
} else if (closest.type == ElementType::GROUP) {
rendererArgs_->hintText = std::string("GROUP\n") + ctx_->getGroupName(closest.group).c_str(ctx_);
rendererArgs_->hintText = std::string("GROUP\n") + ctx_->getGroupName(closest.group).str(ctx_);
} else
rendererArgs_->hintText = "";

2
ice40/delay.cc
View File

@ -80,7 +80,7 @@ void ice40DelayFuzzerMain(Context *ctx)
printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
ctx->getWireType(cursor).c_str(ctx), ctx->getWireName(cursor).c_str(ctx), int(delay),
ctx->getWireType(cursor).c_str(ctx), ctx->nameOfWire(cursor), int(delay),
int(ctx->estimateDelay(cursor, dst)));
if (cursor == src)

9
ice40/pack.cc
View File

@ -417,7 +417,7 @@ static BelId find_padin_gbuf(Context *ctx, BelId bel, IdString port_name)
auto wire = ctx->getBelPinWire(bel, port_name);
if (wire == WireId())
log_error("BEL '%s' has no global buffer connection available\n", ctx->getBelName(bel).c_str(ctx));
log_error("BEL '%s' has no global buffer connection available\n", ctx->nameOfBel(bel));
for (auto src_bel : ctx->getWireBelPins(wire)) {
if (ctx->getBelType(src_bel.bel) == id_SB_GB && src_bel.pin == id_GLOBAL_BUFFER_OUTPUT) {
@ -839,7 +839,7 @@ static void place_plls(Context *ctx)
if (conflict_cell == ci)
continue;
log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
ci->name.c_str(ctx), ctx->nameOfBel(found_bel), conflict_cell->name.c_str(ctx));
}
// Is it user constrained ?
@ -849,8 +849,7 @@ static void place_plls(Context *ctx)
if (bel_constrain != found_bel)
log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
"connection\n",
ci->name.c_str(ctx), ctx->getBelName(bel_constrain).c_str(ctx),
ctx->getBelName(found_bel).c_str(ctx));
ci->name.c_str(ctx), ctx->nameOfBel(bel_constrain), ctx->nameOfBel(found_bel));
} else {
// No, we can constrain it ourselves
ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
@ -999,7 +998,7 @@ static void place_plls(Context *ctx)
log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n", ci->name.c_str(ctx),
could_be_pad ? " Did you mean to use a PAD PLL ?" : "");
log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx));
log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->nameOfBel(found_bel));
if (could_be_pad)
log_info(" (given its connections, this PLL could have been a PAD PLL)\n");