refactor: Replace getXName().c_str(ctx) with ctx->nameOfX
This makes the ongoing migration to IdStringList easier. Signed-off-by: D. Shah <dave@ds0.me>
This commit is contained in:
parent
6d23461bcd
commit
9388df19d3
@ -48,7 +48,7 @@ void archcheck_names(const Context *ctx)
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IdString name = ctx->getWireName(wire);
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IdString name = ctx->getWireName(wire);
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WireId wire2 = ctx->getWireByName(name);
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WireId wire2 = ctx->getWireByName(name);
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if (wire != wire2) {
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if (wire != wire2) {
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log_error("wire != wire2, name = %s\n", name.c_str(ctx));
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log_error("wire != wire2, name = %s\n", ctx->nameOfWire(wire));
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}
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}
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}
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}
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@ -67,7 +67,7 @@ void archcheck_names(const Context *ctx)
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IdString name = ctx->getPipName(pip);
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IdString name = ctx->getPipName(pip);
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PipId pip2 = ctx->getPipByName(name);
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PipId pip2 = ctx->getPipByName(name);
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if (pip != pip2) {
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if (pip != pip2) {
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log_error("pip != pip2, name = %s\n", name.c_str(ctx));
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log_error("pip != pip2, name = %s\n", ctx->nameOfPip(pip));
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}
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}
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}
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}
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#endif
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#endif
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@ -109,7 +109,7 @@ void archcheck_locs(const Context *ctx)
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if (bel == BelId())
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if (bel == BelId())
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continue;
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continue;
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Loc loc = ctx->getBelLocation(bel);
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Loc loc = ctx->getBelLocation(bel);
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dbg(" + %d %s\n", z, ctx->getBelName(bel).c_str(ctx));
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dbg(" + %d %s\n", z, ctx->nameOfBel(bel));
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log_assert(x == loc.x);
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log_assert(x == loc.x);
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log_assert(y == loc.y);
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log_assert(y == loc.y);
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log_assert(z == loc.z);
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log_assert(z == loc.z);
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@ -118,7 +118,7 @@ void archcheck_locs(const Context *ctx)
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for (BelId bel : ctx->getBelsByTile(x, y)) {
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for (BelId bel : ctx->getBelsByTile(x, y)) {
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Loc loc = ctx->getBelLocation(bel);
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Loc loc = ctx->getBelLocation(bel);
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dbg(" - %d %s\n", loc.z, ctx->getBelName(bel).c_str(ctx));
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dbg(" - %d %s\n", loc.z, ctx->nameOfBel(bel));
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log_assert(x == loc.x);
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log_assert(x == loc.x);
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log_assert(y == loc.y);
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log_assert(y == loc.y);
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log_assert(usedz.count(loc.z));
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log_assert(usedz.count(loc.z));
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@ -563,9 +563,9 @@ class SAPlacer
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}
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}
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commit_cost_changes(moveChange);
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commit_cost_changes(moveChange);
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#if 0
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#if 0
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log_info("swap %s -> %s\n", cell->name.c_str(ctx), ctx->getBelName(newBel).c_str(ctx));
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log_info("swap %s -> %s\n", cell->name.c_str(ctx), ctx->nameOfBel(newBel));
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if (other_cell != nullptr)
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if (other_cell != nullptr)
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log_info("swap %s -> %s\n", other_cell->name.c_str(ctx), ctx->getBelName(oldBel).c_str(ctx));
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log_info("swap %s -> %s\n", other_cell->name.c_str(ctx), ctx->nameOfBel(oldBel));
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#endif
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#endif
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return true;
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return true;
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swap_fail:
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swap_fail:
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@ -590,7 +590,7 @@ class SAPlacer
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{
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{
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BelId oldBel = cell->bel;
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BelId oldBel = cell->bel;
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#if 0
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#if 0
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log_info("%s old: %s new: %s\n", cell->name.c_str(ctx), ctx->getBelName(cell->bel).c_str(ctx), ctx->getBelName(newBel).c_str(ctx));
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log_info("%s old: %s new: %s\n", cell->name.c_str(ctx), ctx->nameOfBel(cell->bel), ctx->nameOfBel(newBel));
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#endif
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#endif
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CellInfo *bound = ctx->getBoundBelCell(newBel);
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CellInfo *bound = ctx->getBoundBelCell(newBel);
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if (bound != nullptr)
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if (bound != nullptr)
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@ -885,8 +885,7 @@ void timing_analysis(Context *ctx, bool print_histogram, bool print_fmax, bool p
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auto pip = it->second.pip;
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auto pip = it->second.pip;
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NPNR_ASSERT(pip != PipId());
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NPNR_ASSERT(pip != PipId());
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delay = ctx->getPipDelay(pip).maxDelay();
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delay = ctx->getPipDelay(pip).maxDelay();
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log_info(" %1.3f %s\n", ctx->getDelayNS(delay),
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log_info(" %1.3f %s\n", ctx->getDelayNS(delay), ctx->nameOfPip(pip));
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ctx->getPipName(pip).c_str(ctx));
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cursor = ctx->getPipSrcWire(pip);
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cursor = ctx->getPipSrcWire(pip);
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}
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}
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}
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}
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@ -238,8 +238,7 @@ class Ecp5GlobalRouter
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if (visit.empty() || visit.size() > 50000) {
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if (visit.empty() || visit.size() > 50000) {
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if (allow_fail)
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if (allow_fail)
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return false;
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return false;
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log_error("cannot route global from %s to %s.\n", ctx->getWireName(src).c_str(ctx),
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log_error("cannot route global from %s to %s.\n", ctx->nameOfWire(src), ctx->nameOfWire(dst));
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ctx->getWireName(dst).c_str(ctx));
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}
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}
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cursor = visit.front();
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cursor = visit.front();
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visit.pop();
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visit.pop();
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@ -325,8 +324,8 @@ class Ecp5GlobalRouter
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} else {
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} else {
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// Check for dedicated routing
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// Check for dedicated routing
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if (has_short_route(ctx->getBelPinWire(drv_bel, drv.port), ctx->getBelPinWire(dcc->bel, id_CLKI))) {
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if (has_short_route(ctx->getBelPinWire(drv_bel, drv.port), ctx->getBelPinWire(dcc->bel, id_CLKI))) {
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// log_info("dedicated route %s -> %s\n", ctx->getWireName(ctx->getBelPinWire(drv_bel,
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// log_info("dedicated route %s -> %s\n", ctx->nameOfWire(ctx->getBelPinWire(drv_bel,
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// drv.port)).c_str(ctx), ctx->getBelName(dcc->bel).c_str(ctx));
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// drv.port)), ctx->nameOfWire(dcc->bel));
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dedicated_routing = true;
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dedicated_routing = true;
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return 0;
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return 0;
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}
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}
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@ -347,8 +346,8 @@ class Ecp5GlobalRouter
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while (true) {
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while (true) {
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if (visit.empty() || visit.size() > 10000) {
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if (visit.empty() || visit.size() > 10000) {
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// log_info ("dist %s -> %s = inf\n", ctx->getWireName(src).c_str(ctx),
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// log_info ("dist %s -> %s = inf\n", ctx->nameOfWire(src),
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// ctx->getWireName(dst).c_str(ctx));
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// ctx->nameOfWire(dst));
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return false;
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return false;
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}
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}
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cursor = visit.front();
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cursor = visit.front();
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@ -372,7 +371,7 @@ class Ecp5GlobalRouter
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cursor = ctx->getPipSrcWire(fnd->second);
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cursor = ctx->getPipSrcWire(fnd->second);
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length++;
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length++;
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}
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}
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// log_info ("dist %s -> %s = %d\n", ctx->getWireName(src).c_str(ctx), ctx->getWireName(dst).c_str(ctx),
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// log_info ("dist %s -> %s = %d\n", ctx->nameOfWire(src), ctx->nameOfWire(dst),
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// length);
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// length);
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return length < thresh;
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return length < thresh;
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}
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}
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@ -1853,7 +1853,7 @@ class Ecp5Packer
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next = upstream.front();
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next = upstream.front();
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upstream.pop();
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upstream.pop();
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if (ctx->debug)
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if (ctx->debug)
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log_info(" visited %s\n", ctx->getWireName(next).c_str(ctx));
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log_info(" visited %s\n", ctx->nameOfWire(next));
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IdString basename = ctx->getWireBasename(next);
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IdString basename = ctx->getWireBasename(next);
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if (basename == bnke_name || basename == global_name) {
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if (basename == bnke_name || basename == global_name) {
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break;
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break;
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@ -631,7 +631,7 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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addProperty(portInfoItem, QVariant::String, "Name", item.c_str(ctx));
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addProperty(portInfoItem, QVariant::String, "Name", item.c_str(ctx));
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addProperty(portInfoItem, QVariant::Int, "Type", int(ctx->getBelPinType(bel, item)));
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addProperty(portInfoItem, QVariant::Int, "Type", int(ctx->getBelPinType(bel, item)));
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WireId wire = ctx->getBelPinWire(bel, item);
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WireId wire = ctx->getBelPinWire(bel, item);
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addProperty(portInfoItem, QVariant::String, "Wire", ctx->getWireName(wire).c_str(ctx), ElementType::WIRE);
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addProperty(portInfoItem, QVariant::String, "Wire", ctx->nameOfWire(wire), ElementType::WIRE);
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}
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}
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} else if (type == ElementType::WIRE) {
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} else if (type == ElementType::WIRE) {
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std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
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std::lock_guard<std::mutex> lock_ui(ctx->ui_mutex);
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@ -644,8 +644,8 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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addProperty(topItem, QVariant::String, "Type", ctx->getWireType(wire).c_str(ctx));
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addProperty(topItem, QVariant::String, "Type", ctx->getWireType(wire).c_str(ctx));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkWireAvail(wire));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkWireAvail(wire));
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundWireNet(wire)), ElementType::NET);
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundWireNet(wire)), ElementType::NET);
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addProperty(topItem, QVariant::String, "Conflicting Wire",
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addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingWireWire(wire)),
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ctx->getWireName(ctx->getConflictingWireWire(wire)).c_str(ctx), ElementType::WIRE);
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ElementType::WIRE);
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingWireNet(wire)),
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingWireNet(wire)),
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ElementType::NET);
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ElementType::NET);
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@ -666,7 +666,7 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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for (const auto &item : ctx->getWireBelPins(wire)) {
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for (const auto &item : ctx->getWireBelPins(wire)) {
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QString belname = "";
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QString belname = "";
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if (item.bel != BelId())
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if (item.bel != BelId())
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belname = ctx->getBelName(item.bel).c_str(ctx);
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belname = ctx->nameOfBel(item.bel);
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QString pinname = item.pin.c_str(ctx);
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QString pinname = item.pin.c_str(ctx);
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QtProperty *dhItem = addSubGroup(belpinsItem, belname + "-" + pinname);
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QtProperty *dhItem = addSubGroup(belpinsItem, belname + "-" + pinname);
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@ -707,16 +707,15 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
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addProperty(topItem, QVariant::Bool, "Available", ctx->checkPipAvail(pip));
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
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addProperty(topItem, QVariant::String, "Bound Net", ctx->nameOf(ctx->getBoundPipNet(pip)), ElementType::NET);
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if (ctx->getConflictingPipWire(pip) != WireId()) {
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if (ctx->getConflictingPipWire(pip) != WireId()) {
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addProperty(topItem, QVariant::String, "Conflicting Wire",
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addProperty(topItem, QVariant::String, "Conflicting Wire", ctx->nameOfWire(ctx->getConflictingPipWire(pip)),
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ctx->getWireName(ctx->getConflictingPipWire(pip)).c_str(ctx), ElementType::WIRE);
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ElementType::WIRE);
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} else {
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} else {
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addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
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addProperty(topItem, QVariant::String, "Conflicting Wire", "", ElementType::NONE);
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}
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}
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
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addProperty(topItem, QVariant::String, "Conflicting Net", ctx->nameOf(ctx->getConflictingPipNet(pip)),
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ElementType::NET);
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ElementType::NET);
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addProperty(topItem, QVariant::String, "Src Wire", ctx->getWireName(ctx->getPipSrcWire(pip)).c_str(ctx),
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addProperty(topItem, QVariant::String, "Src Wire", ctx->nameOfWire(ctx->getPipSrcWire(pip)), ElementType::WIRE);
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ElementType::WIRE);
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addProperty(topItem, QVariant::String, "Dest Wire", ctx->nameOfWire(ctx->getPipDstWire(pip)),
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addProperty(topItem, QVariant::String, "Dest Wire", ctx->getWireName(ctx->getPipDstWire(pip)).c_str(ctx),
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ElementType::WIRE);
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ElementType::WIRE);
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QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
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QtProperty *attrsItem = addSubGroup(topItem, "Attributes");
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@ -769,14 +768,13 @@ void DesignWidget::onSelectionChanged(int num, const QItemSelection &, const QIt
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QtProperty *wiresItem = addSubGroup(topItem, "Wires");
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QtProperty *wiresItem = addSubGroup(topItem, "Wires");
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for (auto &item : net->wires) {
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for (auto &item : net->wires) {
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auto name = ctx->getWireName(item.first).c_str(ctx);
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auto name = ctx->nameOfWire(item.first);
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QtProperty *wireItem = addSubGroup(wiresItem, name);
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QtProperty *wireItem = addSubGroup(wiresItem, name);
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addProperty(wireItem, QVariant::String, "Wire", name, ElementType::WIRE);
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addProperty(wireItem, QVariant::String, "Wire", name, ElementType::WIRE);
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if (item.second.pip != PipId())
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if (item.second.pip != PipId())
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addProperty(wireItem, QVariant::String, "Pip", ctx->getPipName(item.second.pip).c_str(ctx),
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addProperty(wireItem, QVariant::String, "Pip", ctx->nameOfPip(item.second.pip), ElementType::PIP);
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ElementType::PIP);
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else
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else
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addProperty(wireItem, QVariant::String, "Pip", "", ElementType::PIP);
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addProperty(wireItem, QVariant::String, "Pip", "", ElementType::PIP);
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@ -779,22 +779,22 @@ void FPGAViewWidget::mouseMoveEvent(QMouseEvent *event)
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rendererArgs_->x = event->x();
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rendererArgs_->x = event->x();
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rendererArgs_->y = event->y();
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rendererArgs_->y = event->y();
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if (closest.type == ElementType::BEL) {
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if (closest.type == ElementType::BEL) {
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rendererArgs_->hintText = std::string("BEL\n") + ctx_->getBelName(closest.bel).c_str(ctx_);
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rendererArgs_->hintText = std::string("BEL\n") + ctx_->getBelName(closest.bel).str(ctx_);
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CellInfo *cell = ctx_->getBoundBelCell(closest.bel);
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CellInfo *cell = ctx_->getBoundBelCell(closest.bel);
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if (cell != nullptr)
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if (cell != nullptr)
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rendererArgs_->hintText += std::string("\nCELL\n") + ctx_->nameOf(cell);
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rendererArgs_->hintText += std::string("\nCELL\n") + ctx_->nameOf(cell);
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} else if (closest.type == ElementType::WIRE) {
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} else if (closest.type == ElementType::WIRE) {
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rendererArgs_->hintText = std::string("WIRE\n") + ctx_->getWireName(closest.wire).c_str(ctx_);
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rendererArgs_->hintText = std::string("WIRE\n") + ctx_->getWireName(closest.wire).str(ctx_);
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NetInfo *net = ctx_->getBoundWireNet(closest.wire);
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NetInfo *net = ctx_->getBoundWireNet(closest.wire);
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if (net != nullptr)
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if (net != nullptr)
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rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
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rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
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} else if (closest.type == ElementType::PIP) {
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} else if (closest.type == ElementType::PIP) {
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rendererArgs_->hintText = std::string("PIP\n") + ctx_->getPipName(closest.pip).c_str(ctx_);
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rendererArgs_->hintText = std::string("PIP\n") + ctx_->getPipName(closest.pip).str(ctx_);
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NetInfo *net = ctx_->getBoundPipNet(closest.pip);
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NetInfo *net = ctx_->getBoundPipNet(closest.pip);
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if (net != nullptr)
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if (net != nullptr)
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rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
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rendererArgs_->hintText += std::string("\nNET\n") + ctx_->nameOf(net);
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} else if (closest.type == ElementType::GROUP) {
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} else if (closest.type == ElementType::GROUP) {
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rendererArgs_->hintText = std::string("GROUP\n") + ctx_->getGroupName(closest.group).c_str(ctx_);
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rendererArgs_->hintText = std::string("GROUP\n") + ctx_->getGroupName(closest.group).str(ctx_);
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} else
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} else
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rendererArgs_->hintText = "";
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rendererArgs_->hintText = "";
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@ -80,7 +80,7 @@ void ice40DelayFuzzerMain(Context *ctx)
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printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
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printf("%s %d %d %s %s %d %d\n", cursor == dst ? "dst" : "src",
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int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
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int(ctx->chip_info->wire_data[cursor.index].x), int(ctx->chip_info->wire_data[cursor.index].y),
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ctx->getWireType(cursor).c_str(ctx), ctx->getWireName(cursor).c_str(ctx), int(delay),
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ctx->getWireType(cursor).c_str(ctx), ctx->nameOfWire(cursor), int(delay),
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int(ctx->estimateDelay(cursor, dst)));
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int(ctx->estimateDelay(cursor, dst)));
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if (cursor == src)
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if (cursor == src)
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@ -417,7 +417,7 @@ static BelId find_padin_gbuf(Context *ctx, BelId bel, IdString port_name)
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auto wire = ctx->getBelPinWire(bel, port_name);
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auto wire = ctx->getBelPinWire(bel, port_name);
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if (wire == WireId())
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if (wire == WireId())
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log_error("BEL '%s' has no global buffer connection available\n", ctx->getBelName(bel).c_str(ctx));
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log_error("BEL '%s' has no global buffer connection available\n", ctx->nameOfBel(bel));
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for (auto src_bel : ctx->getWireBelPins(wire)) {
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for (auto src_bel : ctx->getWireBelPins(wire)) {
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if (ctx->getBelType(src_bel.bel) == id_SB_GB && src_bel.pin == id_GLOBAL_BUFFER_OUTPUT) {
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if (ctx->getBelType(src_bel.bel) == id_SB_GB && src_bel.pin == id_GLOBAL_BUFFER_OUTPUT) {
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@ -839,7 +839,7 @@ static void place_plls(Context *ctx)
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if (conflict_cell == ci)
|
if (conflict_cell == ci)
|
||||||
continue;
|
continue;
|
||||||
log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
|
log_error("PLL '%s' PACKAGEPIN forces it to BEL %s but BEL is already assigned to PLL '%s'\n",
|
||||||
ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx), conflict_cell->name.c_str(ctx));
|
ci->name.c_str(ctx), ctx->nameOfBel(found_bel), conflict_cell->name.c_str(ctx));
|
||||||
}
|
}
|
||||||
|
|
||||||
// Is it user constrained ?
|
// Is it user constrained ?
|
||||||
@ -849,8 +849,7 @@ static void place_plls(Context *ctx)
|
|||||||
if (bel_constrain != found_bel)
|
if (bel_constrain != found_bel)
|
||||||
log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
|
log_error("PLL '%s' is user constrained to %s but can only be placed in %s based on its PACKAGEPIN "
|
||||||
"connection\n",
|
"connection\n",
|
||||||
ci->name.c_str(ctx), ctx->getBelName(bel_constrain).c_str(ctx),
|
ci->name.c_str(ctx), ctx->nameOfBel(bel_constrain), ctx->nameOfBel(found_bel));
|
||||||
ctx->getBelName(found_bel).c_str(ctx));
|
|
||||||
} else {
|
} else {
|
||||||
// No, we can constrain it ourselves
|
// No, we can constrain it ourselves
|
||||||
ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
|
ci->attrs[ctx->id("BEL")] = ctx->getBelName(found_bel).str(ctx);
|
||||||
@ -999,7 +998,7 @@ static void place_plls(Context *ctx)
|
|||||||
log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n", ci->name.c_str(ctx),
|
log_error("PLL '%s' couldn't be placed anywhere, no suitable BEL found.%s\n", ci->name.c_str(ctx),
|
||||||
could_be_pad ? " Did you mean to use a PAD PLL ?" : "");
|
could_be_pad ? " Did you mean to use a PAD PLL ?" : "");
|
||||||
|
|
||||||
log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->getBelName(found_bel).c_str(ctx));
|
log_info(" constrained PLL '%s' to %s\n", ci->name.c_str(ctx), ctx->nameOfBel(found_bel));
|
||||||
if (could_be_pad)
|
if (could_be_pad)
|
||||||
log_info(" (given its connections, this PLL could have been a PAD PLL)\n");
|
log_info(" (given its connections, this PLL could have been a PAD PLL)\n");
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user