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Merge branch 'master' of gitlab.com:SymbioticEDA/nextpnr

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This commit is contained in:
David Shah 2018-06-20 20:14:08 +02:00
commit 93ed8ca405
4 changed files with 45 additions and 16 deletions
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16
common/route.cc
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@ -162,6 +162,22 @@ struct Router
src_wires[src_wire] = 0; src_wires[src_wire] = 0;
route(src_wires, dst_wire); route(src_wires, dst_wire);
routedOkay = visited.count(dst_wire); routedOkay = visited.count(dst_wire);
if (ctx->verbose) {
log("Route (from destination to source):\n");
WireId cursor = dst_wire;
while (1) {
log(" %8.3f %s\n", ctx->getDelayNS(visited[cursor].delay),
ctx->getWireName(cursor).c_str(ctx));
if (cursor == src_wire)
break;
cursor = ctx->getPipSrcWire(visited[cursor].pip);
}
}
} }
Router(Context *ctx, IdString net_name, bool ripup = false, Router(Context *ctx, IdString net_name, bool ripup = false,

18
ice40/arch.cc
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@ -306,14 +306,22 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
delay_t Arch::estimateDelay(WireId src, WireId dst) const delay_t Arch::estimateDelay(WireId src, WireId dst) const
{ {
assert(src != WireId()); assert(src != WireId());
delay_t x1 = chip_info->wire_data[src.index].x; int x1 = chip_info->wire_data[src.index].x;
delay_t y1 = chip_info->wire_data[src.index].y; int y1 = chip_info->wire_data[src.index].y;
assert(dst != WireId()); assert(dst != WireId());
delay_t x2 = chip_info->wire_data[dst.index].x; int x2 = chip_info->wire_data[dst.index].x;
delay_t y2 = chip_info->wire_data[dst.index].y; int y2 = chip_info->wire_data[dst.index].y;
return delay_t(50 * (fabsf(x1 - x2) + fabsf(y1 - y2))); int xd = x2 - x1, yd = y2 - y1;
int xscale = 120, yscale = 120, offset = 0;
// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
// offset = 500;
// }
return xscale * abs(xd) + yscale * abs(yd) + offset;
} }
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------

8
ice40/chipdb.py
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@ -72,10 +72,10 @@ tiletypes["RAMT"] = 4
wiretypes["LOCAL"] = 1 wiretypes["LOCAL"] = 1
wiretypes["GLOBAL"] = 2 wiretypes["GLOBAL"] = 2
wiretypes["SP4_VERT"] = 5 wiretypes["SP4_VERT"] = 3
wiretypes["SP4_HORZ"] = 6 wiretypes["SP4_HORZ"] = 4
wiretypes["SP12_HORZ"] = 7 wiretypes["SP12_HORZ"] = 5
wiretypes["SP12_VERT"] = 8 wiretypes["SP12_VERT"] = 6
def maj_wire_name(name): def maj_wire_name(name):
if name[2].startswith("lutff_"): if name[2].startswith("lutff_"):

19
ice40/main.cc
View File

@ -256,15 +256,20 @@ int main(int argc, char *argv[])
for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size()); for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size());
i++) { i++) {
delay_t actual_delay; delay_t actual_delay;
if (!get_actual_route_delay(&ctx, src_wires[i], dst_wires[i], WireId src = src_wires[i], dst = dst_wires[i];
actual_delay)) if (!get_actual_route_delay(&ctx, src, dst, actual_delay))
continue; continue;
printf("%s %s %.3f %.3f\n", printf("%s %s %.3f %.3f %d %d %d %d %d %d\n",
ctx.getWireName(src_wires[i]).c_str(&ctx), ctx.getWireName(src).c_str(&ctx),
ctx.getWireName(dst_wires[i]).c_str(&ctx), ctx.getWireName(dst).c_str(&ctx),
ctx.getDelayNS(actual_delay), ctx.getDelayNS(actual_delay),
ctx.getDelayNS( ctx.getDelayNS(ctx.estimateDelay(src, dst)),
ctx.estimateDelay(src_wires[i], dst_wires[i]))); ctx.chip_info->wire_data[src.index].x,
ctx.chip_info->wire_data[src.index].y,
ctx.chip_info->wire_data[src.index].type,
ctx.chip_info->wire_data[dst.index].x,
ctx.chip_info->wire_data[dst.index].y,
ctx.chip_info->wire_data[dst.index].type);
} }
} }