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Add clock inversion pip

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This commit is contained in:
Miodrag Milanovic 2025-01-08 15:02:56 +01:00
parent 005bffab48
commit 94071078dc
2 changed files with 9 additions and 0 deletions
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2
himbaechel/uarch/gatemate/bitstream.cc
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@ -164,6 +164,8 @@ struct BitstreamBackend
boost::replace_all(word, "OM.", stringf("OM%d.", x));
if (boost::starts_with(word, "IOES."))
boost::replace_all(word, "IOES.", "IOES1.");
if (boost::starts_with(word, "CPE."))
boost::replace_all(word, "CPE.", stringf("CPE%d.", x));
cc.tiles[loc].add_word(word, int_to_bitvector(extra_data.value, extra_data.bits));
}
}

7
himbaechel/uarch/gatemate/gen/arch_gen.py
View File

@ -94,10 +94,16 @@ def main():
pp.extra_data = PipExtraData(PIP_EXTRA_CPE,ch.strs.id("RAM_O2"))
for i in range(1,9):
tt.create_wire(f"CPE.V_IN{i}", "CPE_VIRTUAL_WIRE")
tt.create_wire("CPE.V_CLK", "CPE_VIRTUAL_WIRE")
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, 0)
pp = tt.create_pip(f"CPE.V_IN{i}", f"CPE.IN{i}")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id(f"CPE.IN{i}_INV"), 1, i, MUX_CPE_INV | MUX_INVERT)
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 1, MUX_VISIBLE)
pp = tt.create_pip("CPE.V_CLK", "CPE.CLK")
pp.extra_data = PipExtraData(PIP_EXTRA_MUX, ch.strs.id("CPE.CLK"), 2, 2, MUX_VISIBLE | MUX_INVERT)
if "GPIO" in type_name:
tt.create_wire("GPIO.OUT_D1", "WIRE_INTERNAL")
tt.create_wire("GPIO.OUT_D2", "WIRE_INTERNAL")
@ -175,6 +181,7 @@ def main():
node = []
for conn in nodes:
conn.name = conn.name.replace("CPE.IN", "CPE.V_IN")
conn.name = conn.name.replace("CPE.CLK", "CPE.V_CLK")
node.append(NodeWire(conn.x + 2, conn.y + 2, conn.name))
ch.add_node(node)
set_timings(ch)