From 946e9f788c90d2a5dc7dd5c758913ae53aba4125 Mon Sep 17 00:00:00 2001 From: Rowan Goemans Date: Thu, 19 Sep 2024 17:23:41 +0200 Subject: [PATCH] timing_log: Fix logging indendation to match master timing: Disable clock_skew analysis by default --- common/kernel/timing.cc | 13 +++++++------ common/kernel/timing.h | 4 ++-- common/kernel/timing_log.cc | 12 ++++++------ 3 files changed, 15 insertions(+), 14 deletions(-) diff --git a/common/kernel/timing.cc b/common/kernel/timing.cc index ce4ef9a0..7ca6c3d2 100644 --- a/common/kernel/timing.cc +++ b/common/kernel/timing.cc @@ -715,7 +715,8 @@ dict TimingAnalyser::max_delay_by_domain_pairs() // walk back to startpoint auto crit_path = walk_crit_path(domain_pair_id(launch_id, capture_id), ep.first, true); - auto &sp = crit_path.back(); + auto first_inp = crit_path.back(); + const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver; auto &sp_port = ports.at(CellPortKey{sp.cell->name, sp.port}); for (auto &fanin : sp_port.cell_arcs) { @@ -877,9 +878,8 @@ std::vector TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel // We store the reversed critical path as all input ports that lead to // the timing startpoint. auto is_input = portClass != TMG_CLOCK_INPUT && portClass != TMG_IGNORE && port.type == PortType::PORT_IN; - is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT; - if (is_input || is_startpoint) + if (is_input) crit_path_rev.emplace_back(PortRef{cell, port.name}); if (!ports.at(cursor).arrival.count(dp.key.launch)) @@ -890,6 +890,7 @@ std::vector TimingAnalyser::walk_crit_path(domain_id_t domain_pair, Cel } else { cursor = ports.at(cursor).arrival.at(dp.key.launch).bwd_min; } + is_startpoint = portClass == TMG_REGISTER_OUTPUT || portClass == TMG_STARTPOINT; } while (!is_startpoint); return crit_path_rev; @@ -930,7 +931,8 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, auto crit_path = boost::adaptors::reverse(crit_path_rev); // Get timing and clocking info on the startpoint - const auto &sp = crit_path.front(); + auto first_inp = crit_path.front(); + const auto &sp = first_inp.cell->ports.at(first_inp.port).net->driver; const auto &sp_cell = sp.cell; const auto &sp_port = sp_cell->ports.at(sp.port); int sp_clocks; @@ -1037,8 +1039,7 @@ CriticalPath TimingAnalyser::build_critical_path_report(domain_id_t domain_pair, if (is_startpoint && register_start) { comb_delay = sp_clk_info.clockToQ; seg_logic.type = CriticalPath::Segment::Type::CLK_TO_Q; - } else if (prev_port == driver.port) { - // Case where we start with a STARTPOINT etc + } else if (is_startpoint) { comb_delay = DelayQuad(0); seg_logic.type = CriticalPath::Segment::Type::SOURCE; } else { diff --git a/common/kernel/timing.h b/common/kernel/timing.h index 9bba709e..a6222a2e 100644 --- a/common/kernel/timing.h +++ b/common/kernel/timing.h @@ -99,8 +99,8 @@ struct TimingAnalyser TimingResult &get_timing_result() { return result; } // Enable analysis of clock skew between FFs. - // Only do this after legal placement - bool with_clock_skew = true; + bool with_clock_skew = false; + // REMOVE ME once approved delay_t clock_delay_fac = 100; diff --git a/common/kernel/timing_log.cc b/common/kernel/timing_log.cc index 77db543b..825d209c 100644 --- a/common/kernel/timing_log.cc +++ b/common/kernel/timing_log.cc @@ -61,9 +61,9 @@ static void log_crit_paths(const Context *ctx, TimingResult &result) source_entries.emplace_back(sourcelist.substr(prev, current - prev)); // Iterate and print our source list at the correct indentation level - log_info(" Defined in:\n"); + log_info(" Defined in:\n"); for (auto entry : source_entries) { - log_info(" %s\n", entry.c_str()); + log_info(" %s\n", entry.c_str()); } }; @@ -82,7 +82,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result) return ctx->getDelayNS(d.maxDelay()); }; - log_info(" type curr total\n"); + log_info(" type curr total name\n"); for (const auto &segment : path.segments) { total += segment.delay; @@ -94,7 +94,7 @@ static void log_crit_paths(const Context *ctx, TimingResult &result) segment.type == CriticalPath::Segment::Type::HOLD) { logic_total += segment.delay; - log_info("%10s % 5.2f % 5.2f %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(), + log_info("%10s % 5.2f % 5.2f Source %s.%s\n", CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay), get_delay_ns(total), segment.to.first.c_str(ctx), segment.to.second.c_str(ctx)); } else if (segment.type == CriticalPath::Segment::Type::ROUTING || @@ -108,11 +108,11 @@ static void log_crit_paths(const Context *ctx, TimingResult &result) auto driver_loc = ctx->getBelLocation(driver->bel); auto sink_loc = ctx->getBelLocation(sink->bel); - log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n", + log_info("%10s % 5.2f % 5.2f Net %s (%d,%d) -> (%d,%d)\n", CriticalPath::Segment::type_to_str(segment.type).c_str(), get_delay_ns(segment.delay), get_delay_ns(total), segment.net.c_str(ctx), driver_loc.x, driver_loc.y, sink_loc.x, sink_loc.y); - log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), + log_info(" Sink %s.%s\n", segment.to.first.c_str(ctx), segment.to.second.c_str(ctx)); const NetInfo *net = ctx->nets.at(segment.net).get();