Improve --tmfuzz mode and iCE40 delay estimator
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
2da90889ef
commit
9475997a2d
@ -162,6 +162,22 @@ struct Router
|
||||
src_wires[src_wire] = 0;
|
||||
route(src_wires, dst_wire);
|
||||
routedOkay = visited.count(dst_wire);
|
||||
|
||||
if (ctx->verbose) {
|
||||
log("Route (from destination to source):\n");
|
||||
|
||||
WireId cursor = dst_wire;
|
||||
|
||||
while (1) {
|
||||
log(" %8.3f %s\n", ctx->getDelayNS(visited[cursor].delay),
|
||||
ctx->getWireName(cursor).c_str(ctx));
|
||||
|
||||
if (cursor == src_wire)
|
||||
break;
|
||||
|
||||
cursor = ctx->getPipSrcWire(visited[cursor].pip);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
Router(Context *ctx, IdString net_name, bool ripup = false,
|
||||
|
@ -306,14 +306,22 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
|
||||
delay_t Arch::estimateDelay(WireId src, WireId dst) const
|
||||
{
|
||||
assert(src != WireId());
|
||||
delay_t x1 = chip_info->wire_data[src.index].x;
|
||||
delay_t y1 = chip_info->wire_data[src.index].y;
|
||||
int x1 = chip_info->wire_data[src.index].x;
|
||||
int y1 = chip_info->wire_data[src.index].y;
|
||||
|
||||
assert(dst != WireId());
|
||||
delay_t x2 = chip_info->wire_data[dst.index].x;
|
||||
delay_t y2 = chip_info->wire_data[dst.index].y;
|
||||
int x2 = chip_info->wire_data[dst.index].x;
|
||||
int y2 = chip_info->wire_data[dst.index].y;
|
||||
|
||||
return fabsf(x1 - x2) + fabsf(y1 - y2);
|
||||
int xd = x2 - x1, yd = y2 - y1;
|
||||
int xscale = 120, yscale = 120, offset = 0;
|
||||
|
||||
// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
|
||||
// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
|
||||
// offset = 500;
|
||||
// }
|
||||
|
||||
return xscale * abs(xd) + yscale * abs(yd) + offset;
|
||||
}
|
||||
|
||||
// -----------------------------------------------------------------------
|
||||
|
@ -72,10 +72,10 @@ tiletypes["RAMT"] = 4
|
||||
|
||||
wiretypes["LOCAL"] = 1
|
||||
wiretypes["GLOBAL"] = 2
|
||||
wiretypes["SP4_VERT"] = 5
|
||||
wiretypes["SP4_HORZ"] = 6
|
||||
wiretypes["SP12_HORZ"] = 7
|
||||
wiretypes["SP12_VERT"] = 8
|
||||
wiretypes["SP4_VERT"] = 3
|
||||
wiretypes["SP4_HORZ"] = 4
|
||||
wiretypes["SP12_HORZ"] = 5
|
||||
wiretypes["SP12_VERT"] = 6
|
||||
|
||||
def maj_wire_name(name):
|
||||
if name[2].startswith("lutff_"):
|
||||
|
@ -248,15 +248,20 @@ int main(int argc, char *argv[])
|
||||
for (int i = 0; i < int(src_wires.size()) && i < int(dst_wires.size());
|
||||
i++) {
|
||||
delay_t actual_delay;
|
||||
if (!get_actual_route_delay(&ctx, src_wires[i], dst_wires[i],
|
||||
actual_delay))
|
||||
WireId src = src_wires[i], dst = dst_wires[i];
|
||||
if (!get_actual_route_delay(&ctx, src, dst, actual_delay))
|
||||
continue;
|
||||
printf("%s %s %.3f %.3f\n",
|
||||
ctx.getWireName(src_wires[i]).c_str(&ctx),
|
||||
ctx.getWireName(dst_wires[i]).c_str(&ctx),
|
||||
printf("%s %s %.3f %.3f %d %d %d %d %d %d\n",
|
||||
ctx.getWireName(src).c_str(&ctx),
|
||||
ctx.getWireName(dst).c_str(&ctx),
|
||||
ctx.getDelayNS(actual_delay),
|
||||
ctx.getDelayNS(
|
||||
ctx.estimateDelay(src_wires[i], dst_wires[i])));
|
||||
ctx.getDelayNS(ctx.estimateDelay(src, dst)),
|
||||
ctx.chip_info->wire_data[src.index].x,
|
||||
ctx.chip_info->wire_data[src.index].y,
|
||||
ctx.chip_info->wire_data[src.index].type,
|
||||
ctx.chip_info->wire_data[dst.index].x,
|
||||
ctx.chip_info->wire_data[dst.index].y,
|
||||
ctx.chip_info->wire_data[dst.index].type);
|
||||
}
|
||||
}
|
||||
|
||||
|
Loading…
Reference in New Issue
Block a user