cleanup: Spelling fixes

Signed-off-by: D. Shah <dave@ds0.me>

common/placer1.cc

@@ -406,7 +406,7 @@ class SAPlacer
         auto saplace_end = std::chrono::high_resolution_clock::now();
         log_info("SA placement time %.02fs\n", std::chrono::duration<float>(saplace_end - saplace_start).count());
 
-        // Final post-pacement validitiy check
+        // Final post-placement validity check
         ctx->yield();
         for (auto bel : ctx->getBels()) {
             CellInfo *cell = ctx->getBoundBelCell(bel);
@@ -548,7 +548,7 @@ class SAPlacer
             goto swap_fail;
         }
 
-        // Recalculate metrics for all nets touched by the peturbation
+        // Recalculate metrics for all nets touched by the perturbation
         compute_cost_changes(moveChange);
 
         new_dist = get_constraints_distance(ctx, cell);
@@ -560,7 +560,7 @@ class SAPlacer
         if (cfg.netShareWeight > 0)
             delta += -cfg.netShareWeight * (net_delta_score / std::max<double>(total_net_share, epsilon));
         n_move++;
-        // SA acceptance criterea
+        // SA acceptance criteria
         if (delta < 0 || (temp > 1e-8 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
             n_accept++;
         } else {
@@ -691,7 +691,7 @@ class SAPlacer
                     cfg.netShareWeight * (orig_share_cost - total_net_share) / std::max<double>(total_net_share, 1e-20);
         }
         n_move++;
-        // SA acceptance criterea
+        // SA acceptance criteria
         if (delta < 0 || (temp > 1e-9 && (ctx->rng() / float(0x3fffffff)) <= std::exp(-delta / temp))) {
             n_accept++;
 #if 0

common/placer_heap.cc

@@ -195,8 +195,8 @@ class HeAPPlacer
             }
 
         if (cfg.placeAllAtOnce) {
-            // Never want to deal with LUTs, FFs, MUXFxs seperately,
+            // Never want to deal with LUTs, FFs, MUXFxs separately,
-            // for now disable all single-cell-type runs and only have heteregenous
+            // for now disable all single-cell-type runs and only have heterogeneous
             // runs
             heap_runs.clear();
         }
@@ -205,7 +205,7 @@ class HeAPPlacer
         // The main HeAP placer loop
         log_info("Running main analytical placer.\n");
         while (stalled < 5 && (solved_hpwl <= legal_hpwl * 0.8)) {
-            // Alternate between particular Bel types and all bels
+            // Alternate between particular bel types and all bels
             for (auto &run : heap_runs) {
                 auto run_startt = std::chrono::high_resolution_clock::now();
 
@@ -321,7 +321,7 @@ class HeAPPlacer
     std::vector<std::vector<std::vector<std::vector<BelId>>>> fast_bels;
     std::unordered_map<IdString, std::tuple<int, int>> bel_types;
 
-    // For fast handling of heterogeneosity during initial placement without full legalisation,
+    // For fast handling of heterogeneity during initial placement without full legalisation,
     // for each Bel type this goes from x or y to the nearest x or y where a Bel of a given type exists
     // This is particularly important for the iCE40 architecture, where multipliers and BRAM only exist at the
     // edges and corners respectively
@@ -1595,7 +1595,7 @@ class HeAPPlacer
                 std::accumulate(right_bels_v.begin(), right_bels_v.end(), 0) == 0)
                 return {};
 
-            // Peturb the source cut to eliminate overutilisation
+            // Perturb the source cut to eliminate overutilisation
             auto is_part_overutil = [&](bool r) {
                 double delta = 0;
                 for (size_t t = 0; t < left_cells_v.size(); t++) {

common/router2.cc

@@ -412,7 +412,7 @@ struct Router2
         WireId cursor = sink;
         bool done = false;
         if (ctx->debug)
-            log("resevering wires for arc %d of net %s\n", int(i), ctx->nameOf(net));
+            log("reserving wires for arc %d of net %s\n", int(i), ctx->nameOf(net));
         while (!done) {
             auto &wd = wire_data(cursor);
             if (ctx->debug)

common/timing.cc

@@ -317,7 +317,8 @@ struct Timing
                             auto &data = net_data[port.second.net][start_clk];
                             auto &arrival = data.max_arrival;
                             arrival = std::max(arrival, usr_arrival + comb_delay.maxDelay());
-                            if (!budget_override) { // Do not increment path length if budget overriden since it doesn't
+                            if (!budget_override) { // Do not increment path length if budget overridden since it
+                                                    // doesn't
                                 // require a share of the slack
                                 auto &path_length = data.max_path_length;
                                 path_length = std::max(path_length, net_length_plus_one);

docs/archapi.md

@@ -320,8 +320,8 @@ Get the source wire for a pip.
 
 Get the destination wire for a pip.
 
-Bi-directional switches (transfer gates) are modelled using two
+Bi-directional switches (transfer gates) are modeled using two
-antiparallel pips.
+anti-parallel pips.
 
 ### DelayInfo getPipDelay(PipId pip) const
 
@@ -378,8 +378,8 @@ This should return a low upper bound for the fastest route from `src` to `dst`.
 
 Or in other words it should assume an otherwise unused chip (thus "fastest route").
 But it only produces an estimate for that fastest route, not an exact 
-result, and for that estimate it is considered more accaptable to return a
+result, and for that estimate it is considered more acceptable to return a
-slightly too high result and it is considered less accaptable to return a
+slightly too high result and it is considered less acceptable to return a
 too low result (thus "low upper bound").
 
 ### delay\_t predictDelay(const NetInfo \*net\_info, const PortRef &sink) const

docs/coding.md

@@ -32,7 +32,7 @@ Additionally to this; architectures provide functions for checking the availabil
 
 To avoid the high cost of using strings as identifiers directly; almost all "string" identifiers in nextpnr (such as cell names and types) use an indexed string pool type named `IdString`. Unlike Yosys, which has a global garbage collected pool, nextpnr has a per-Context pool without any garbage collection. 
 
-`IdString`s can be created in two ways. Architectures can add `IdString`s with constant indicies - allowing `IdString` constants to be provided too - using `initialize_add` at startup. See how `constids.inc` is used in iCE40 for an example of this. The main way to create `IdString`s, however, is at runtime using the `id` member function of `BaseCtx` given the string to create from (if an `IdString` of that string already exists, the existing `IdString` will be returned).
+`IdString`s can be created in two ways. Architectures can add `IdString`s with constant indices - allowing `IdString` constants to be provided too - using `initialize_add` at startup. See how `constids.inc` is used in iCE40 for an example of this. The main way to create `IdString`s, however, is at runtime using the `id` member function of `BaseCtx` given the string to create from (if an `IdString` of that string already exists, the existing `IdString` will be returned).
 
 Note that `IdString`s need a `Context` (or `BaseCtx`) pointer to convert them back to regular strings, due to the pool being per-context as described above.
 

docs/faq.md

@@ -57,7 +57,7 @@ for your architecture once implementing small designs work.
 The `getConflictingWireWire()`, `getConflictingWireNet()`, `getConflictingPipWire()`, and `getConflictingPipNet()` methods are used by the router
 to determine which resources to rip up in order to make a given routing resource (wire or pip) available.
 
-The architecture must guanrantee that the following invariants hold.
+The architecture must guarantee that the following invariants hold.
 
 **Invariant 1:**
 
@@ -223,4 +223,4 @@ for these parts.
 
 As the open source community now has support for multiple different FPGA parts,
 in the nextpnr documentation we generally use Project IceStorm to mean the database and
-tools that fulfil the same role as Project Trellis or Project X-Ray.
+tools that fulfill the same role as Project Trellis or Project X-Ray.

ecp5/bitstream.cc

@@ -527,7 +527,7 @@ static std::vector<bool> parse_config_str(const Property &p, int length)
     std::vector<bool> word;
     if (p.is_string) {
         std::string str = p.as_string();
-        // For DCU config which might be bin, hex or dec using prefices accordingly
+        // For DCU config which might be bin, hex or dec using prefixes accordingly
         std::string base = str.substr(0, 2);
         word.resize(length, false);
         if (base == "0b") {

ecp5/pack.cc

@@ -1126,7 +1126,7 @@ class Ecp5Packer
         flush_cells();
     }
 
-    // Find a cell that meets some criterea near an origin cell
+    // Find a cell that meets some criteria near an origin cell
     // Used for packing an FF into a nearby SLICE
     template <typename TFunc> CellInfo *find_nearby_cell(CellInfo *origin, TFunc Func)
     {

gui/fpgaviewwidget.cc

@@ -158,7 +158,7 @@ float FPGAViewWidget::PickedElement::distance(Context *ctx, float wx, float wy)
                            return std::abs(dw - dab) / dab;
                        }
                        default:
-                           // Not close to antyhing.
+                           // Not close to anything.
                            return -1;
                        }
                    });
@@ -819,7 +819,7 @@ QVector4D FPGAViewWidget::mouseToWorldCoordinates(int x, int y)
     vec = projection.inverted() * QVector4D(vec.x(), vec.y(), -1, 1);
 
     // Hic sunt dracones.
-    // TODO(q3k): grab a book, remind yourselfl linear algebra and undo this
+    // TODO(q3k): grab a book, remind yourself linear algebra and undo this
     // operation properly.
     QVector3D ray = vec.toVector3DAffine();
     ray.normalize();

gui/lineshader.cc

@@ -26,7 +26,7 @@ void PolyLine::buildPoint(LineShaderData *building, const QVector2D *prev, const
                           const QVector2D *next) const
 {
     // buildPoint emits two vertices per line point, along with normals to move
-    // them the right directio when rendering and miter to compensate for
+    // them the right direction when rendering and miter to compensate for
     // bends.
 
     if (cur == nullptr) {
@@ -104,7 +104,7 @@ void PolyLine::build(LineShaderData &target) const
 
     // For every point on the line, call buildPoint with (prev, point, next).
     // If we're building a closed line, prev/next wrap around. Otherwise
-    // they are passed as nullptr and buildPoint interprets that accordinglu.
+    // they are passed as nullptr and buildPoint interprets that accordingly.
     const QVector2D *prev = nullptr;
 
     // Loop iterator used to ensure next is valid.

gui/quadtree.h

@@ -20,7 +20,7 @@
 #ifndef QUADTREE_H
 #define QUADTREE_H
 
-// This file implements a quad tree used for comitting 2D axis aligned
+// This file implements a quad tree used for committing 2D axis aligned
 // bounding boxes and then retrieving them by 2D point.
 
 NEXTPNR_NAMESPACE_BEGIN
@@ -382,17 +382,17 @@ template <typename CoordinateT, typename ElementT> class QuadTree
 
     // Standard constructor.
     //
-    // @param b Bounding box of the entire tree - all comitted elements must
+    // @param b Bounding box of the entire tree - all committed elements must
     //          fit within in.
     QuadTree(BoundingBox b) : root_(b, 0) {}
 
     // Inserts a new value at a given bounding box.e
     // BoundingBoxes are not deduplicated - if two are pushed with the same
-    // coordinates, the first one will take precendence.
+    // coordinates, the first one will take precedence.
     //
     // @param k Bounding box at which to store value.
     // @param v Value at a given bounding box.
-    // @returns Whether the insert was succesful.
+    // @returns Whether the insert was successful.
     bool insert(BoundingBox k, ElementT v)
     {
         k.fixup();

gui/treemodel.h

@@ -145,7 +145,7 @@ class IdStringList : public Item
     ElementType child_type_;
 
   public:
-    // Create an IdStringList at given partent that will contain elements of
+    // Create an IdStringList at given parent that will contain elements of
     // the given type.
     IdStringList(ElementType type) : Item("root", nullptr), child_type_(type) {}
 

ice40/arch.h

@@ -833,7 +833,7 @@ struct Arch : BaseCtx
     bool logicCellsCompatible(const CellInfo **it, const size_t size) const;
 
     // -------------------------------------------------
-    // Assign architecure-specific arguments to nets and cells, which must be
+    // Assign architecture-specific arguments to nets and cells, which must be
     // called between packing or further
     // netlist modifications, and validity checks
     void assignArchInfo();

nexus/arch.h

@@ -1354,7 +1354,7 @@ struct Arch : BaseCtx
     void post_place_opt();
 
     // -------------------------------------------------
-    // Assign architecure-specific arguments to nets and cells, which must be
+    // Assign architecture-specific arguments to nets and cells, which must be
     // called between packing or further
     // netlist modifications, and validity checks
     void assignArchInfo();