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Move all string data into BBA file.

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Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2021-02-05 09:22:55 -08:00
parent ca32e935a6
commit 9557047e5e
5 changed files with 16 additions and 48901 deletions
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1
.gitignore vendored
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@ -4,6 +4,7 @@
/nextpnr-ice40*
/nextpnr-ecp5*
/nextpnr-nexus*
/nextpnr-fpga_interchange*
cmake-build-*/
Makefile
cmake_install.cmake

16
fpga_interchange/arch.cc
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@ -45,14 +45,7 @@ static std::pair<std::string, std::string> split_identifier_name_dot(const std::
// -----------------------------------------------------------------------
void IdString::initialize_arch(const BaseCtx *ctx)
{
#define X(t) initialize_add(ctx, #t, ID_##t);
#include "constids.inc"
#undef X
}
void IdString::initialize_arch(const BaseCtx *ctx) {}
// -----------------------------------------------------------------------
@ -70,6 +63,13 @@ Arch::Arch(ArchArgs args) : args(args)
log_error("Unable to read chipdb %s\n", args.chipdb.c_str());
}
// Read strings from constids into IdString database, checking that list
// is unique and matches expected constid value.
int id = 1;
for (const auto &constid : *chip_info->constids) {
IdString::initialize_add(this, constid.get(), id++);
}
tileStatus.resize(chip_info->tiles.size());
for (int i = 0; i < chip_info->tiles.size(); i++) {
tileStatus[i].boundcells.resize(chip_info->tile_types[chip_info->tiles[i].type].bel_data.size());

13
fpga_interchange/arch.h
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@ -152,9 +152,7 @@ NPNR_PACKED_STRUCT(struct TileWireRefPOD {
int32_t index;
});
NPNR_PACKED_STRUCT(struct NodeInfoPOD {
RelSlice<TileWireRefPOD> tile_wires;
});
NPNR_PACKED_STRUCT(struct NodeInfoPOD { RelSlice<TileWireRefPOD> tile_wires; });
NPNR_PACKED_STRUCT(struct CellMapPOD {
// Cell names supported in this arch.
@ -178,6 +176,8 @@ NPNR_PACKED_STRUCT(struct ChipInfoPOD {
RelSlice<int32_t> bel_buckets;
RelPtr<CellMapPOD> cell_map;
RelPtr<RelSlice<RelPtr<char>>> constids;
});
/************************ End of chipdb section. ************************/
@ -192,7 +192,8 @@ template <typename Id> const TileTypeInfoPOD &loc_info(const ChipInfoPOD *chip_i
return chip_info->tile_types[chip_info->tiles[id.tile].type];
}
inline const BelInfoPOD &bel_info(const ChipInfoPOD *chip_info, BelId bel) {
inline const BelInfoPOD &bel_info(const ChipInfoPOD *chip_info, BelId bel)
{
NPNR_ASSERT(bel != BelId());
return loc_info(chip_info, bel).bel_data[bel.index];
}
@ -850,8 +851,8 @@ struct Arch : BaseCtx
{
NPNR_ASSERT(wire != WireId());
if (wire.tile != -1) {
const auto & tile_type = loc_info(chip_info, wire);
if(tile_type.wire_data[wire.index].site != -1) {
const auto &tile_type = loc_info(chip_info, wire);
if (tile_type.wire_data[wire.index].site != -1) {
int site_index = tile_type.wire_data[wire.index].site;
const SiteInstInfoPOD &site = chip_info->sites[chip_info->tiles[wire.tile].sites[site_index]];
std::array<IdString, 2> ids{id(site.name.get()), IdString(tile_type.wire_data[wire.index].name)};

18
fpga_interchange/archdefs.h
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@ -51,24 +51,6 @@ struct DelayInfo
// -----------------------------------------------------------------------
// https://bugreports.qt.io/browse/QTBUG-80789
#ifndef Q_MOC_RUN
enum ConstIds
{
ID_NONE
#define X(t) , ID_##t
#include "constids.inc"
#undef X
};
#define X(t) static constexpr auto id_##t = IdString(ID_##t);
#include "constids.inc"
#undef X
#endif
struct BelId
{
// Tile that contains this BEL.

48869
fpga_interchange/constids.inc
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