Merge branch 'YosysHQ:master' into hclk_support2s
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commit
95594c0fec
@ -782,8 +782,10 @@ bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
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bool GowinImpl::slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const bool lut_in_4_5 = lut && (z == 4 || z == 5);
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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const CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z)));
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// There are only 6 ALUs
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const CellInfo *alu = (z < 6) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z))) : nullptr;
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const CellInfo *ramw =
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(z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
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@ -792,7 +794,7 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
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}
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if (ramw) {
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if (alu || ff || lut) {
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if (alu || ff || lut_in_4_5) {
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return false;
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}
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return true;
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@ -803,7 +805,9 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
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int adj_alu_z = adj_lut_z / 2 + BelZ::ALU0_Z;
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const CellInfo *adj_lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z)));
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const CellInfo *adj_ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_lut_z + 1)));
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const CellInfo *adj_alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)));
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const CellInfo *adj_alu = adj_alu_z < (6 + BelZ::ALU0_Z)
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? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, adj_alu_z)))
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: nullptr;
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if ((alu && (adj_lut || (adj_ff && !adj_alu))) || ((lut || (ff && !alu)) && adj_alu)) {
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return false;
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