diff --git a/ecp5/arch.cc b/ecp5/arch.cc
index 7d67dd0c..ea8abc0e 100644
--- a/ecp5/arch.cc
+++ b/ecp5/arch.cc
@@ -192,14 +192,14 @@ BelId Arch::getBelByName(IdString name) const
     return ret;
 }
 
-BelRange Arch::getBelsAtSameTile(BelId bel) const
+BelRange Arch::getBelsByTile(int x, int y) const
 {
     BelRange br;
-    NPNR_ASSERT(bel != BelId());
-    br.b.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
-    br.e.cursor_tile = bel.location.y * chip_info->width + bel.location.x;
+
+    br.b.cursor_tile = y * chip_info->width + x;
+    br.e.cursor_tile = y * chip_info->width + x;
     br.b.cursor_index = 0;
-    br.e.cursor_index = locInfo(bel)->num_bels - 1;
+    br.e.cursor_index = chip_info->locations[chip_info->location_type[br.b.cursor_tile]].num_bels - 1;
     br.b.chip = chip_info;
     br.e.chip = chip_info;
     ++br.e;
@@ -399,36 +399,8 @@ BelId Arch::getBelByLocation(Loc loc) const
     return BelId();
 }
 
-BelRange Arch::getBelsByTile(int x, int y) const
-{
-    BelRange br;
-
-    int num_bels = 0;
-
-    if (x < chip_info->width && y < chip_info->height) {
-        const LocationTypePOD &locI = chip_info->locations[chip_info->location_type[y * chip_info->width + x]];
-        num_bels = locI.num_bels;
-    }
-
-    br.b.cursor_tile = y * chip_info->width + x;
-    br.e.cursor_tile = y * chip_info->width + x;
-    br.b.cursor_index = 0;
-    br.e.cursor_index = num_bels - 1;
-    br.b.chip = chip_info;
-    br.e.chip = chip_info;
-    ++br.e;
-    return br;
-}
-
 // -----------------------------------------------------------------------
 
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
-    x = bel.location.x;
-    y = bel.location.y;
-    gb = false;
-}
-
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
diff --git a/ecp5/arch.h b/ecp5/arch.h
index ce2b90c3..4400db5e 100644
--- a/ecp5/arch.h
+++ b/ecp5/arch.h
@@ -482,8 +482,6 @@ struct Arch : BaseCtx
         return range;
     }
 
-    BelRange getBelsAtSameTile(BelId bel) const;
-
     BelType getBelType(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
@@ -752,7 +750,6 @@ struct Arch : BaseCtx
 
     // -------------------------------------------------
 
-    void estimatePosition(BelId bel, int &x, int &y, bool &gb) const;
     delay_t estimateDelay(WireId src, WireId dst) const;
     delay_t getDelayEpsilon() const { return 20; }
     delay_t getRipupDelayPenalty() const { return 200; }
diff --git a/ecp5/arch_place.cc b/ecp5/arch_place.cc
index 22ebab67..84432043 100644
--- a/ecp5/arch_place.cc
+++ b/ecp5/arch_place.cc
@@ -66,7 +66,8 @@ bool Arch::isBelLocationValid(BelId bel) const
 {
     if (getBelType(bel) == TYPE_TRELLIS_SLICE) {
         std::vector<const CellInfo *> bel_cells;
-        for (auto bel_other : getBelsAtSameTile(bel)) {
+        Loc bel_loc = getBelLocation(bel);
+        for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
             IdString cell_other = getBoundBelCell(bel_other);
             if (cell_other != IdString()) {
                 const CellInfo *ci_other = cells.at(cell_other).get();
@@ -89,8 +90,8 @@ bool Arch::isValidBelForCell(CellInfo *cell, BelId bel) const
         NPNR_ASSERT(getBelType(bel) == TYPE_TRELLIS_SLICE);
 
         std::vector<const CellInfo *> bel_cells;
-
-        for (auto bel_other : getBelsAtSameTile(bel)) {
+        Loc bel_loc = getBelLocation(bel);
+        for (auto bel_other : getBelsByTile(bel_loc.x, bel_loc.y)) {
             IdString cell_other = getBoundBelCell(bel_other);
             if (cell_other != IdString() && bel_other != bel) {
                 const CellInfo *ci_other = cells.at(cell_other).get();
diff --git a/generic/arch.cc b/generic/arch.cc
index 0fff2e4c..af245a4b 100644
--- a/generic/arch.cc
+++ b/generic/arch.cc
@@ -368,13 +368,6 @@ const std::vector<GroupId> &Arch::getGroupGroups(GroupId group) const { return g
 
 // ---------------------------------------------------------------
 
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
-    x = bels.at(bel).x;
-    y = bels.at(bel).y;
-    gb = bels.at(bel).gb;
-}
-
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     const WireInfo &s = wires.at(src);
diff --git a/generic/arch.h b/generic/arch.h
index 61e6b033..3025bda0 100644
--- a/generic/arch.h
+++ b/generic/arch.h
@@ -191,7 +191,6 @@ struct Arch : BaseCtx
     const std::vector<PipId> &getGroupPips(GroupId group) const;
     const std::vector<GroupId> &getGroupGroups(GroupId group) const;
 
-    void estimatePosition(BelId bel, int &x, int &y, bool &gb) const;
     delay_t estimateDelay(WireId src, WireId dst) const;
     delay_t getDelayEpsilon() const { return 0.01; }
     delay_t getRipupDelayPenalty() const { return 1.0; }
diff --git a/ice40/arch.cc b/ice40/arch.cc
index c29673cc..2270fdc1 100644
--- a/ice40/arch.cc
+++ b/ice40/arch.cc
@@ -291,23 +291,6 @@ BelRange Arch::getBelsByTile(int x, int y) const
     return br;
 }
 
-BelRange Arch::getBelsAtSameTile(BelId bel) const
-{
-    BelRange br;
-    NPNR_ASSERT(bel != BelId());
-    int x = chip_info->bel_data[bel.index].x;
-    int y = chip_info->bel_data[bel.index].y;
-    int start = bel.index, end = bel.index;
-    while (start >= 0 && chip_info->bel_data[start].x == x && chip_info->bel_data[start].y == y)
-        start--;
-    start++;
-    br.b.cursor = start;
-    while (end < chip_info->num_bels && chip_info->bel_data[end].x == x && chip_info->bel_data[end].y == y)
-        end++;
-    br.e.cursor = end;
-    return br;
-}
-
 PortType Arch::getBelPinType(BelId bel, PortPin pin) const
 {
     NPNR_ASSERT(bel != BelId());
@@ -482,14 +465,6 @@ std::vector<GroupId> Arch::getGroupGroups(GroupId group) const
 
 // -----------------------------------------------------------------------
 
-void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
-{
-    NPNR_ASSERT(bel != BelId());
-    x = chip_info->bel_data[bel.index].x;
-    y = chip_info->bel_data[bel.index].y;
-    gb = chip_info->bel_data[bel.index].type == TYPE_SB_GB;
-}
-
 delay_t Arch::estimateDelay(WireId src, WireId dst) const
 {
     NPNR_ASSERT(src != WireId());
diff --git a/ice40/arch.h b/ice40/arch.h
index 3f6a5324..3aec25a2 100644
--- a/ice40/arch.h
+++ b/ice40/arch.h
@@ -449,8 +449,6 @@ struct Arch : BaseCtx
 
     bool getBelGlobalBuf(BelId bel) const { return chip_info->bel_data[bel.index].type == TYPE_SB_GB; }
 
-    BelRange getBelsAtSameTile(BelId bel) const NPNR_DEPRECATED;
-
     BelType getBelType(BelId bel) const
     {
         NPNR_ASSERT(bel != BelId());
@@ -681,7 +679,6 @@ struct Arch : BaseCtx
 
     // -------------------------------------------------
 
-    void estimatePosition(BelId bel, int &x, int &y, bool &gb) const NPNR_DEPRECATED;
     delay_t estimateDelay(WireId src, WireId dst) const;
     delay_t getDelayEpsilon() const { return 20; }
     delay_t getRipupDelayPenalty() const { return 200; }
diff --git a/ice40/arch_pybindings.cc b/ice40/arch_pybindings.cc
index 246d0f57..98164e87 100644
--- a/ice40/arch_pybindings.cc
+++ b/ice40/arch_pybindings.cc
@@ -79,8 +79,6 @@ void arch_wrap_python()
                   conv_to_str<IdString>, conv_from_str<BelId>>::def_wrap(ctx_cls, "getConflictingBelCell");
     fn_wrapper_0a<Context, decltype(&Context::getBels), &Context::getBels, wrap_context<BelRange>>::def_wrap(ctx_cls,
                                                                                                              "getBels");
-    fn_wrapper_1a<Context, decltype(&Context::getBelsAtSameTile), &Context::getBelsAtSameTile, wrap_context<BelRange>,
-                  conv_from_str<BelId>>::def_wrap(ctx_cls, "getBelsAtSameTile");
 
     fn_wrapper_2a<Context, decltype(&Context::getBelPinWire), &Context::getBelPinWire, conv_to_str<WireId>,
                   conv_from_str<BelId>, conv_from_str<PortPin>>::def_wrap(ctx_cls, "getBelPinWire");