ecp5: Blinky example places and routes
Signed-off-by: David Shah <davey1576@gmail.com>
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@ -218,11 +218,14 @@ WireId Arch::getWireByName(IdString name) const
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for (int i = 0; i < loci->num_wires; i++) {
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if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) {
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ret.index = i;
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ret.location = loc;
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break;
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}
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}
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if (ret.index >= 0)
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wire_by_name[name] = ret;
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else
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ret.location = Location();
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return ret;
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}
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@ -278,7 +281,10 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
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gb = false;
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}
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delay_t Arch::estimateDelay(WireId src, WireId dst) const { return 1; }
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delay_t Arch::estimateDelay(WireId src, WireId dst) const
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{
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return abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y);
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}
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// -----------------------------------------------------------------------
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11
ecp5/synth/wire.v
Normal file
11
ecp5/synth/wire.v
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@ -0,0 +1,11 @@
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module top(input a_pin, output [3:0] led_pin);
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wire a;
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wire [3:0] led;
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TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
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TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led));
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//assign led[0] = !a;
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always @(posedge a) led[0] <= !led[0];
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endmodule
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9
ecp5/synth/wire.ys
Normal file
9
ecp5/synth/wire.ys
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@ -0,0 +1,9 @@
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read_verilog wire.v
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read_verilog -lib cells.v
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synth -top top
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abc -lut 4
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techmap -map simple_map.v
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splitnets
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opt_clean
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stat
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write_json wire.json
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