ecp5: Blinky example places and routes

Signed-off-by: David Shah <davey1576@gmail.com>

ecp5/arch.cc

@@ -218,11 +218,14 @@ WireId Arch::getWireByName(IdString name) const
     for (int i = 0; i < loci->num_wires; i++) {
         if (std::strcmp(loci->wire_data[i].name.get(), basename.c_str()) == 0) {
             ret.index = i;
+            ret.location = loc;
             break;
         }
     }
     if (ret.index >= 0)
         wire_by_name[name] = ret;
+    else
+        ret.location = Location();
     return ret;
 }
 
@@ -278,7 +281,10 @@ void Arch::estimatePosition(BelId bel, int &x, int &y, bool &gb) const
     gb = false;
 }
 
-delay_t Arch::estimateDelay(WireId src, WireId dst) const { return 1; }
+delay_t Arch::estimateDelay(WireId src, WireId dst) const
+{
+    return abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y);
+}
 
 // -----------------------------------------------------------------------
 

ecp5/synth/wire.v

@@ -0,0 +1,11 @@
+module top(input a_pin, output [3:0] led_pin);
+
+	wire a;
+	wire [3:0] led;
+
+	TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
+	TRELLIS_IO #(.DIR("OUTPUT")) led_buf [3:0] (.B(led_pin), .I(led));
+
+    //assign led[0] = !a;
+    always @(posedge a) led[0] <= !led[0];
+endmodule

ecp5/synth/wire.ys

@@ -0,0 +1,9 @@
+read_verilog wire.v
+read_verilog -lib cells.v
+synth -top top
+abc -lut 4
+techmap -map simple_map.v
+splitnets
+opt_clean
+stat
+write_json wire.json