machxo2: Remove generic API functions from Arch.
This commit is contained in:
William D. Jones
gatecat
parent
78880e1fdf
commit
98214865be
230
machxo2/arch.cc
230
machxo2/arch.cc
@ -28,236 +28,6 @@
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NEXTPNR_NAMESPACE_BEGIN
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WireInfo &Arch::wire_info(IdString wire)
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{
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auto w = wires.find(wire);
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if (w == wires.end())
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NPNR_ASSERT_FALSE_STR("no wire named " + wire.str(this));
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return w->second;
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}
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PipInfo &Arch::pip_info(IdString pip)
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{
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auto p = pips.find(pip);
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if (p == pips.end())
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NPNR_ASSERT_FALSE_STR("no pip named " + pip.str(this));
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return p->second;
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}
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BelInfo &Arch::bel_info(IdString bel)
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{
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auto b = bels.find(bel);
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if (b == bels.end())
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NPNR_ASSERT_FALSE_STR("no bel named " + bel.str(this));
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return b->second;
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}
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void Arch::addWire(IdString name, IdString type, int x, int y)
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{
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NPNR_ASSERT(wires.count(name) == 0);
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WireInfo &wi = wires[name];
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wi.name = name;
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wi.type = type;
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wi.x = x;
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wi.y = y;
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wire_ids.push_back(name);
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}
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void Arch::addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc)
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{
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NPNR_ASSERT(pips.count(name) == 0);
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PipInfo &pi = pips[name];
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pi.name = name;
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pi.type = type;
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pi.srcWire = srcWire;
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pi.dstWire = dstWire;
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pi.delay = delay;
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pi.loc = loc;
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wire_info(srcWire).downhill.push_back(name);
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wire_info(dstWire).uphill.push_back(name);
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pip_ids.push_back(name);
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if (int(tilePipDimZ.size()) <= loc.x)
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tilePipDimZ.resize(loc.x + 1);
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if (int(tilePipDimZ[loc.x].size()) <= loc.y)
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tilePipDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tilePipDimZ[loc.x][loc.y] = std::max(tilePipDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay)
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{
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NPNR_ASSERT(pips.count(name) == 0);
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PipInfo &pi = pips[name];
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pi.name = name;
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pi.type = type;
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pi.srcWire = srcWire;
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pi.dstWire = dstWire;
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pi.delay = delay;
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wire_info(srcWire).aliases.push_back(name);
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pip_ids.push_back(name);
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}
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void Arch::addBel(IdString name, IdString type, Loc loc, bool gb)
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{
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NPNR_ASSERT(bels.count(name) == 0);
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NPNR_ASSERT(bel_by_loc.count(loc) == 0);
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BelInfo &bi = bels[name];
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bi.name = name;
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bi.type = type;
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bi.x = loc.x;
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bi.y = loc.y;
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bi.z = loc.z;
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bi.gb = gb;
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bel_ids.push_back(name);
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bel_by_loc[loc] = name;
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if (int(bels_by_tile.size()) <= loc.x)
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bels_by_tile.resize(loc.x + 1);
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if (int(bels_by_tile[loc.x].size()) <= loc.y)
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bels_by_tile[loc.x].resize(loc.y + 1);
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bels_by_tile[loc.x][loc.y].push_back(name);
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if (int(tileBelDimZ.size()) <= loc.x)
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tileBelDimZ.resize(loc.x + 1);
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if (int(tileBelDimZ[loc.x].size()) <= loc.y)
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tileBelDimZ[loc.x].resize(loc.y + 1);
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gridDimX = std::max(gridDimX, loc.x + 1);
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gridDimY = std::max(gridDimY, loc.x + 1);
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tileBelDimZ[loc.x][loc.y] = std::max(tileBelDimZ[loc.x][loc.y], loc.z + 1);
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}
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void Arch::addBelInput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_IN;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelOutput(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_OUT;
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wire_info(wire).uphill_bel_pin = BelPin{bel, name};
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addBelInout(IdString bel, IdString name, IdString wire)
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{
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NPNR_ASSERT(bel_info(bel).pins.count(name) == 0);
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PinInfo &pi = bel_info(bel).pins[name];
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pi.name = name;
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pi.wire = wire;
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pi.type = PORT_INOUT;
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wire_info(wire).downhill_bel_pins.push_back(BelPin{bel, name});
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wire_info(wire).bel_pins.push_back(BelPin{bel, name});
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}
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void Arch::addGroupBel(IdString group, IdString bel) { groups[group].bels.push_back(bel); }
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void Arch::addGroupWire(IdString group, IdString wire) { groups[group].wires.push_back(wire); }
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void Arch::addGroupPip(IdString group, IdString pip) { groups[group].pips.push_back(pip); }
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void Arch::addGroupGroup(IdString group, IdString grp) { groups[group].groups.push_back(grp); }
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void Arch::addDecalGraphic(DecalId decal, const GraphicElement &graphic)
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{
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decal_graphics[decal].push_back(graphic);
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refreshUi();
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}
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void Arch::setWireDecal(WireId wire, DecalXY decalxy)
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{
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wire_info(wire).decalxy = decalxy;
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refreshUiWire(wire);
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}
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void Arch::setPipDecal(PipId pip, DecalXY decalxy)
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{
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pip_info(pip).decalxy = decalxy;
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refreshUiPip(pip);
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}
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void Arch::setBelDecal(BelId bel, DecalXY decalxy)
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{
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bel_info(bel).decalxy = decalxy;
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refreshUiBel(bel);
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}
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void Arch::setGroupDecal(GroupId group, DecalXY decalxy)
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{
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groups[group].decalxy = decalxy;
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refreshUiGroup(group);
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}
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void Arch::setWireAttr(IdString wire, IdString key, const std::string &value) { wire_info(wire).attrs[key] = value; }
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void Arch::setPipAttr(IdString pip, IdString key, const std::string &value) { pip_info(pip).attrs[key] = value; }
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void Arch::setBelAttr(IdString bel, IdString key, const std::string &value) { bel_info(bel).attrs[key] = value; }
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void Arch::setLutK(int K) { args.K = K; }
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void Arch::setDelayScaling(double scale, double offset)
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{
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args.delayScale = scale;
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args.delayOffset = offset;
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}
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void Arch::addCellTimingClock(IdString cell, IdString port) { cellTiming[cell].portClasses[port] = TMG_CLOCK_INPUT; }
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void Arch::addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay)
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{
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if (get_or_default(cellTiming[cell].portClasses, fromPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[fromPort] = TMG_COMB_INPUT;
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if (get_or_default(cellTiming[cell].portClasses, toPort, TMG_IGNORE) == TMG_IGNORE)
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cellTiming[cell].portClasses[toPort] = TMG_COMB_OUTPUT;
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cellTiming[cell].combDelays[CellDelayKey{fromPort, toPort}] = delay;
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}
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void Arch::addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.setup = setup;
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ci.hold = hold;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_INPUT;
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}
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void Arch::addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq)
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{
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TimingClockingInfo ci;
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ci.clock_port = clock;
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ci.edge = RISING_EDGE;
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ci.clockToQ = clktoq;
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cellTiming[cell].clockingInfo[port].push_back(ci);
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cellTiming[cell].portClasses[port] = TMG_REGISTER_OUTPUT;
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}
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// ---------------------------------------------------------------
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Arch::Arch(ArchArgs args) : chipName("generic"), args(args)
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@ -140,38 +140,6 @@ struct Arch : BaseCtx
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std::unordered_map<IdString, CellTiming> cellTiming;
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void addWire(IdString name, IdString type, int x, int y);
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void addPip(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay, Loc loc);
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void addAlias(IdString name, IdString type, IdString srcWire, IdString dstWire, DelayInfo delay);
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void addBel(IdString name, IdString type, Loc loc, bool gb);
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void addBelInput(IdString bel, IdString name, IdString wire);
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void addBelOutput(IdString bel, IdString name, IdString wire);
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void addBelInout(IdString bel, IdString name, IdString wire);
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void addGroupBel(IdString group, IdString bel);
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void addGroupWire(IdString group, IdString wire);
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void addGroupPip(IdString group, IdString pip);
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void addGroupGroup(IdString group, IdString grp);
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void addDecalGraphic(DecalId decal, const GraphicElement &graphic);
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void setWireDecal(WireId wire, DecalXY decalxy);
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void setPipDecal(PipId pip, DecalXY decalxy);
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void setBelDecal(BelId bel, DecalXY decalxy);
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void setGroupDecal(GroupId group, DecalXY decalxy);
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void setWireAttr(IdString wire, IdString key, const std::string &value);
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void setPipAttr(IdString pip, IdString key, const std::string &value);
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void setBelAttr(IdString bel, IdString key, const std::string &value);
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void setLutK(int K);
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void setDelayScaling(double scale, double offset);
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void addCellTimingClock(IdString cell, IdString port);
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void addCellTimingDelay(IdString cell, IdString fromPort, IdString toPort, DelayInfo delay);
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void addCellTimingSetupHold(IdString cell, IdString port, IdString clock, DelayInfo setup, DelayInfo hold);
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void addCellTimingClockToOut(IdString cell, IdString port, IdString clock, DelayInfo clktoq);
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// ---------------------------------------------------------------
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// Common Arch API. Every arch must provide the following methods.
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