caiyu/nextpnr
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

ecp5: Bitstream progress

Browse Source 
Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-07-10 11:57:58 +02:00
parent 29d65bd368
commit 98cdb6082d
4 changed files with 9 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
ecp5/bitstream.cc
View File

@ -187,7 +187,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
for (const auto &tile : empty_chip.tiles) {
std::string type = tile.second->info.type;
if (type.find("BANKREF") != std::string::npos && type != "BANKREF8") {
cc.tiles[type].add_enum("BANK.VCCIO", "3V3");
cc.tiles[tile.first].add_enum("BANK.VCCIO", "3V3");
}
}

2
ecp5/synth/cells.v
View File

@ -27,7 +27,7 @@ parameter CCU2_INJECT1_1 = "NO";
endmodule
(* blackbox *)
(* blackbox *) (* keep *)
module TRELLIS_IO(
inout B,
input I,

6
ecp5/synth/simple_map.v
View File

@ -25,7 +25,7 @@ module \$lut (A, Y);
if (WIDTH == 1) begin
TRELLIS_SLICE #(
.MODE("LOGIC"),
.LUT0_INITVAL(LUT)
.LUT0_INITVAL({8{LUT[1:0]}})
) _TECHMAP_REPLACE_ (
.A0(A[0]),
.F0(Y)
@ -34,7 +34,7 @@ module \$lut (A, Y);
if (WIDTH == 2) begin
TRELLIS_SLICE #(
.MODE("LOGIC"),
.LUT0_INITVAL(LUT)
.LUT0_INITVAL({4{LUT[3:0]}})
) _TECHMAP_REPLACE_ (
.A0(A[0]),
.B0(A[1]),
@ -44,7 +44,7 @@ module \$lut (A, Y);
if (WIDTH == 3) begin
TRELLIS_SLICE #(
.MODE("LOGIC"),
.LUT0_INITVAL(LUT)
.LUT0_INITVAL({2{LUT[7:0]}})
) _TECHMAP_REPLACE_ (
.A0(A[0]),
.B0(A[1]),

9
ecp5/synth/ulx3s.v
View File

@ -3,14 +3,13 @@ module top(input a_pin, output led_pin, output gpio0_pin);
wire a;
wire led;
wire gpio0;
(* BEL="X90/Y65/PIOB" *) (* IO_TYPE="LVCMOS33" *)
(* BEL="X6/Y0/PIOB" *) (* IO_TYPE="LVCMOS33" *)
TRELLIS_IO #(.DIR("INPUT")) a_buf (.B(a_pin), .O(a));
(* BEL="X0/Y23/PIOC" *) (* IO_TYPE="LVCMOS33" *)
TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led), .T(t));
TRELLIS_IO #(.DIR("OUTPUT")) led_buf (.B(led_pin), .I(led));
(* BEL="X0/Y62/PIOD" *) (* IO_TYPE="LVCMOS33" *)
TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0), .T(t));
TRELLIS_IO #(.DIR("OUTPUT")) gpio0_buf (.B(gpio0_pin), .I(gpio0));
assign led = !a;
wire t;
TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'h0000)) gnd (.F0(t));
TRELLIS_SLICE #(.MODE("LOGIC"), .LUT0_INITVAL(16'hFFFF)) vcc (.F0(gpio0));
endmodule