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ecp5: Preparations for new IO bels

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Signed-off-by: David Shah <dave@ds0.me>
This commit is contained in:
David Shah 2019-10-09 10:55:10 +01:00
parent e9cced57bf
commit 9b83e67460
3 changed files with 16 additions and 1 deletions
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4
ecp5/arch.cc
View File

@ -889,6 +889,10 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
if (cell->ports.at(port).name == id_STOP)
return TMG_ENDPOINT;
return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
} else if (cell->type == id_ECLKBRIDGECS) {
if (cell->ports.at(port).name == id_SEL)
return TMG_ENDPOINT;
return (cell->ports.at(port).type == PORT_OUT) ? TMG_COMB_OUTPUT : TMG_COMB_INPUT;
} else {
log_error("cell type '%s' is unsupported (instantiated as '%s')\n", cell->type.c_str(this),
cell->name.c_str(this));

7
ecp5/bitstream.cc
View File

@ -1367,6 +1367,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
if (get_net_or_empty(ci, id_STOP) != nullptr)
cc.tiles[tile].add_enum(eclksync + ".MODE", "ECLKSYNCB");
} else if (ci->type == id_ECLKBRIDGECS) {
Loc loc = ctx->getBelLocation(ci->bel);
bool r = loc.x > 5;
std::string eclkb = ctx->locInfo(bel)->bel_data[bel.index].name.get();
std::string tile = ctx->getTileByType(std::string("ECLK_") + (r ? "R" : "L"));
if (get_net_or_empty(ci, id_STOP) != nullptr)
cc.tiles[tile].add_enum(eclkb + ".MODE", "ECLKBRIDGECS");
} else if (ci->type == id_DDRDLL) {
Loc loc = ctx->getBelLocation(ci->bel);
bool u = loc.y<15, r = loc.x> 15;

6
ecp5/constids.inc
View File

@ -1288,4 +1288,8 @@ X(MULT18X18D_REGS_INPUT)
X(MULT18X18D_REGS_NONE)
X(MULT18X18D_REGS_OUTPUT)
X(MULT18X18D_REGS_PIPELINE)
X(P)
X(P)
X(ECLKBRIDGECS)
X(SEL)
X(ECSOUT)