diff --git a/himbaechel/uarch/ng-ultra/location_map.cc b/himbaechel/uarch/ng-ultra/location_map.cc index a4140a91..0a83379c 100644 --- a/himbaechel/uarch/ng-ultra/location_map.cc +++ b/himbaechel/uarch/ng-ultra/location_map.cc @@ -21,7 +21,9 @@ NEXTPNR_NAMESPACE_BEGIN -static const Loc ng_ultra_place_cy_map[24] = { +namespace { + +const Loc ng_ultra_place_cy_map[24] = { { 0, 1, 0 }, // S1 0 -> S2 0 CY24->CY1 { 0, 0, -1 }, // S1 1 -> S1 0 CY23->CY24 { 0, 0, -1 }, // S1 2 -> S1 1 CY22->CY23 @@ -53,7 +55,7 @@ static const Loc ng_ultra_place_cy_map[24] = { {0,-1, 0}, // S10 3 -> S9 3 CY12->CY13 }; -static const Loc ng_ultra_place_xrf[] = +const Loc ng_ultra_place_xrf[] = { {-1, 0, 1},// I/O1 {-1, 0, 2},// I/O2 @@ -118,7 +120,7 @@ static const Loc ng_ultra_place_xrf[] = }; -static const Loc ng_ultra_place_cdc1[] = +const Loc ng_ultra_place_cdc1[] = { {+1, 0, 1}, // AI1 {+1, 0, 2}, // AI2 @@ -140,7 +142,7 @@ static const Loc ng_ultra_place_cdc1[] = {+1, 0, 8}, // BDRSTI }; -static const Loc ng_ultra_place_cdc2[] = +const Loc ng_ultra_place_cdc2[] = { {-1, 0, 4}, // AI1 {-1, 0, 5}, // AI2 @@ -162,7 +164,7 @@ static const Loc ng_ultra_place_cdc2[] = {-1, 0, 7}, // BDRSTI }; -static const Loc ng_ultra_place_xcdc[] = +const Loc ng_ultra_place_xcdc[] = { { 0, 0, 1}, // AI1 { 0, 0, 2}, // AI2 @@ -203,7 +205,7 @@ static const Loc ng_ultra_place_xcdc[] = { 0, 0, 7}, // DDRSTI }; -static const Loc ng_ultra_place_fifo1[] = +const Loc ng_ultra_place_fifo1[] = { {-1, 0, 1}, // I/O1 {-1, 0, 2}, // I/O2 @@ -283,7 +285,7 @@ static const Loc ng_ultra_place_fifo1[] = { 0, 0, 0}, // REQ2 }; -static const Loc ng_ultra_place_fifo2[] = +const Loc ng_ultra_place_fifo2[] = { {+1, 0, 1}, // I/O1 {+1, 0, 2}, // I/O2 @@ -363,7 +365,7 @@ static const Loc ng_ultra_place_fifo2[] = { 0, 0, 0}, // REQ2 }; -static const Loc ng_ultra_place_xfifo[] = +const Loc ng_ultra_place_xfifo[] = { {-1, 0, 1}, // I/O1 {-1, 0, 2}, // I/O2 @@ -448,6 +450,10 @@ static const Loc ng_ultra_place_xfifo[] = // {+1, 0, 28}, REQ2 }; +}; + +namespace ng_ultra { + Loc getNextLocInDSPChain(const NgUltraImpl *impl, Loc loc) { BelId bel = impl->ctx->getBelByLocation(loc); @@ -533,4 +539,5 @@ Loc getFIFOFE(Loc root, int pos) return result; } +}; NEXTPNR_NAMESPACE_END diff --git a/himbaechel/uarch/ng-ultra/location_map.h b/himbaechel/uarch/ng-ultra/location_map.h index 36c98c2e..0547260a 100644 --- a/himbaechel/uarch/ng-ultra/location_map.h +++ b/himbaechel/uarch/ng-ultra/location_map.h @@ -25,6 +25,8 @@ NEXTPNR_NAMESPACE_BEGIN +namespace ng_ultra { + Loc getNextLocInDSPChain(const NgUltraImpl *impl, Loc loc); Loc getNextLocInCYChain(Loc loc); Loc getCYFE(Loc root, int pos); @@ -33,5 +35,7 @@ Loc getXRFFE(Loc root, int pos); Loc getCDCFE(Loc root, int pos); Loc getFIFOFE(Loc root, int pos); +}; + NEXTPNR_NAMESPACE_END #endif diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc index 41dfce64..cbdff63c 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.cc +++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc @@ -37,6 +37,7 @@ #define GEN_INIT_CONSTIDS #define HIMBAECHEL_CONSTIDS "uarch/ng-ultra/constids.inc" #include "himbaechel_constids.h" +using namespace NEXTPNR_NAMESPACE_PREFIX ng_ultra; NEXTPNR_NAMESPACE_BEGIN @@ -75,7 +76,7 @@ void NgUltraImpl::init(Context *ctx) } std::pair p; p.first = *ckg.begin(); - if (ckg.size()==2) p.second = *ckg.end(); + if (ckg.size()==2) p.second = *(ckg.begin()++); bank_to_ckg[bank] = p; } else if (ctx->getBelType(bel) == id_IOTP) { if (ctx->getBelName(bel)[1] == ctx->id("D08P_CLK.IOTP")) { @@ -85,8 +86,8 @@ void NgUltraImpl::init(Context *ctx) } } else if (ctx->getBelType(bel) == id_GCK) { std::string name = ctx->getBelName(bel)[1].c_str(ctx); - int lobe = name[1] - '0'; - int num = atoi(name.substr(4,2).c_str()); + int lobe = std::stoi(name.substr(1,1)); + int num = std::stoi(name.substr(4,2).c_str()); gck_per_lobe[lobe].insert(gck_per_lobe[lobe].begin()+num-1, GckConfig(bel)); } locations.emplace(stringf("%s:%s",tile_name(bel.tile).c_str(), ctx->getBelName(bel)[1].c_str(ctx)),bel); @@ -106,136 +107,109 @@ void NgUltraImpl::init(Context *ctx) } } } +} - // Note: These are per Cell type not Bel type - // Sinks +namespace { +// Note: These are per Cell type not Bel type +// Sinks +const dict> fabric_clock_sinks = { // TILE - DFF - fabric_clock_sinks[id_BEYOND_FE].insert(id_CK); - //fabric_clock_sinks[id_DFF].insert(id_CK); // This is part of BEYOND_FE + { id_BEYOND_FE, { id_CK }}, + // { id_DFF, { id_CK }}, // This is part of BEYOND_FE // TILE - Register file - fabric_clock_sinks[id_RF].insert(id_WCK); - fabric_clock_sinks[id_RFSP].insert(id_WCK); - fabric_clock_sinks[id_XHRF].insert(id_WCK1); - fabric_clock_sinks[id_XHRF].insert(id_WCK2); - fabric_clock_sinks[id_XWRF].insert(id_WCK1); - fabric_clock_sinks[id_XWRF].insert(id_WCK2); - fabric_clock_sinks[id_XPRF].insert(id_WCK1); - fabric_clock_sinks[id_XPRF].insert(id_WCK2); + { id_RF, { id_WCK }}, + { id_RFSP, { id_WCK }}, + { id_XHRF, { id_WCK1, id_WCK2 }}, + { id_XWRF, { id_WCK1, id_WCK2 }}, + { id_XPRF, { id_WCK1, id_WCK2 }}, // TILE - CDC - fabric_clock_sinks[id_CDC].insert(id_CK1); - fabric_clock_sinks[id_CDC].insert(id_CK2); - fabric_clock_sinks[id_DDE].insert(id_CK1); - fabric_clock_sinks[id_DDE].insert(id_CK2); - fabric_clock_sinks[id_TDE].insert(id_CK1); - fabric_clock_sinks[id_TDE].insert(id_CK2); - fabric_clock_sinks[id_XCDC].insert(id_CK1); - fabric_clock_sinks[id_XCDC].insert(id_CK2); + { id_CDC, { id_CK1, id_CK2 }}, + { id_DDE, { id_CK1, id_CK2 }}, + { id_TDE, { id_CK1, id_CK2 }}, + { id_XCDC, { id_CK1, id_CK2 }}, // TILE - FIFO - fabric_clock_sinks[id_FIFO].insert(id_RCK); - fabric_clock_sinks[id_FIFO].insert(id_WCK); - fabric_clock_sinks[id_XHFIFO].insert(id_RCK1); - fabric_clock_sinks[id_XHFIFO].insert(id_RCK2); - fabric_clock_sinks[id_XHFIFO].insert(id_WCK1); - fabric_clock_sinks[id_XHFIFO].insert(id_WCK2); - fabric_clock_sinks[id_XWFIFO].insert(id_RCK1); - fabric_clock_sinks[id_XWFIFO].insert(id_RCK2); - fabric_clock_sinks[id_XWFIFO].insert(id_WCK1); - fabric_clock_sinks[id_XWFIFO].insert(id_WCK2); + { id_FIFO, { id_RCK, id_WCK }}, + { id_XHFIFO, { id_RCK1, id_RCK2, id_WCK1, id_WCK2 }}, + { id_XWFIFO, { id_RCK1, id_RCK2, id_WCK1, id_WCK2 }}, // CGB - RAM - fabric_clock_sinks[id_RAM].insert(id_ACK); - fabric_clock_sinks[id_RAM].insert(id_BCK); + { id_RAM, { id_ACK, id_BCK }}, // CGB - DSP - fabric_clock_sinks[id_DSP].insert(id_CK); + { id_DSP, {id_CK }}, +}; +const dict> ring_clock_sinks = { // CKG - ring_clock_sinks[id_PLL].insert(id_CLK_CAL); - ring_clock_sinks[id_PLL].insert(id_FBK); - ring_clock_sinks[id_PLL].insert(id_REF); - ring_clock_sinks[id_WFB].insert(id_ZI); - ring_clock_sinks[id_WFG].insert(id_ZI); + { id_PLL, { id_CLK_CAL, id_FBK, id_REF }}, + { id_WFB, { id_ZI }}, + { id_WFG, { id_ZI }} +}; +const dict> ring_over_tile_clock_sinks = { // IOB - ring_over_tile_clock_sinks[id_DFR].insert(id_CK); - ring_over_tile_clock_sinks[id_DDFR].insert(id_CK); - ring_over_tile_clock_sinks[id_DDFR].insert(id_CKF); - // ring_clock_sinks[id_IOM].insert(id_ALCK1); - // ring_clock_sinks[id_IOM].insert(id_ALCK2); - // ring_clock_sinks[id_IOM].insert(id_ALCK3); - // ring_clock_sinks[id_IOM].insert(id_CCK); - // ring_clock_sinks[id_IOM].insert(id_FCK1); - // ring_clock_sinks[id_IOM].insert(id_FCK2); - // ring_clock_sinks[id_IOM].insert(id_FDCK); - // ring_clock_sinks[id_IOM].insert(id_LDSCK1); - // ring_clock_sinks[id_IOM].insert(id_LDSCK2); - // ring_clock_sinks[id_IOM].insert(id_LDSCK3); - // ring_clock_sinks[id_IOM].insert(id_SWRX1CK); - // ring_clock_sinks[id_IOM].insert(id_SWRX2CK); + { id_DFR, { id_CK }}, + { id_DDFR, { id_CK }}, + { id_DDFR, { id_CKF }}, +}; + // IOB + // { id_IOM, { id_ALCK1, id_ALCK2, id_ALCK3, id_CCK, id_FCK1, id_FCK2, id_FDCK, + // id_LDSCK1, id_LDSCK2, id_LDSCK3, id_SWRX1CK, id_SWRX2CK }}, // HSSL - // ring_clock_sinks[id_CRX].insert(id_LINK); - // ring_clock_sinks[id_CTX].insert(id_LINK); - // ring_clock_sinks[id_PMA].insert(id_hssl_clock_i1); - // ring_clock_sinks[id_PMA].insert(id_hssl_clock_i2); - // ring_clock_sinks[id_PMA].insert(id_hssl_clock_i3); - // ring_clock_sinks[id_PMA].insert(id_hssl_clock_i4); - + // { id_CRX, { id_LINK }}, + // { id_CTX, { id_LINK }}, + // { id_PMA, { id_hssl_clock_i1, id_hssl_clock_i2, id_hssl_clock_i3, id_hssl_clock_i4 }, + +const dict> tube_clock_sinks = { // TUBE - tube_clock_sinks[id_GCK].insert(id_SI1); - tube_clock_sinks[id_GCK].insert(id_SI2); + { id_GCK, { id_SI1, id_SI2 }}, +}; // Sources // CKG - ring_clock_source[id_IOM].insert(id_CKO1); - ring_clock_source[id_IOM].insert(id_CKO2); - ring_clock_source[id_WFB].insert(id_ZO); - ring_clock_source[id_WFG].insert(id_ZO); - ring_clock_source[id_PLL].insert(id_OSC); - ring_clock_source[id_PLL].insert(id_VCO); - ring_clock_source[id_PLL].insert(id_REFO); - ring_clock_source[id_PLL].insert(id_LDFO); - ring_clock_source[id_PLL].insert(id_CLK_DIV1); - ring_clock_source[id_PLL].insert(id_CLK_DIV2); - ring_clock_source[id_PLL].insert(id_CLK_DIV3); - ring_clock_source[id_PLL].insert(id_CLK_DIV4); - ring_clock_source[id_PLL].insert(id_CLK_DIVD1); - ring_clock_source[id_PLL].insert(id_CLK_DIVD2); - ring_clock_source[id_PLL].insert(id_CLK_DIVD3); - ring_clock_source[id_PLL].insert(id_CLK_DIVD4); - ring_clock_source[id_PLL].insert(id_CLK_DIVD5); - ring_clock_source[id_PLL].insert(id_CLK_CAL_DIV); - +const dict> ring_clock_source = { + { id_IOM, { id_CKO1, id_CKO2 }}, + { id_WFB, { id_ZO }}, + { id_WFG, { id_ZO }}, + { id_PLL, { id_OSC, id_VCO, id_REFO, id_LDFO, + id_CLK_DIV1, id_CLK_DIV2, id_CLK_DIV3, id_CLK_DIV4, + id_CLK_DIVD1, id_CLK_DIVD2, id_CLK_DIVD3, id_CLK_DIVD4, id_CLK_DIVD5, + id_CLK_CAL_DIV }} +}; // TUBE - tube_clock_source[id_GCK].insert(id_SO); -} +const dict> tube_clock_source = { + { id_GCK, { id_SO }}, +}; + +}; bool NgUltraImpl::is_fabric_clock_sink(const PortRef &ref) { - return fabric_clock_sinks.count(ref.cell->type) && fabric_clock_sinks[ref.cell->type].count(ref.port); + return fabric_clock_sinks.count(ref.cell->type) && fabric_clock_sinks.at(ref.cell->type).count(ref.port); } bool NgUltraImpl::is_ring_clock_sink(const PortRef &ref) { - return ring_clock_sinks.count(ref.cell->type) && ring_clock_sinks[ref.cell->type].count(ref.port); + return ring_clock_sinks.count(ref.cell->type) && ring_clock_sinks.at(ref.cell->type).count(ref.port); } bool NgUltraImpl::is_ring_over_tile_clock_sink(const PortRef &ref) { - return ring_over_tile_clock_sinks.count(ref.cell->type) && ring_over_tile_clock_sinks[ref.cell->type].count(ref.port); + return ring_over_tile_clock_sinks.count(ref.cell->type) && ring_over_tile_clock_sinks.at(ref.cell->type).count(ref.port); } bool NgUltraImpl::is_tube_clock_sink(const PortRef &ref) { - return tube_clock_sinks.count(ref.cell->type) && tube_clock_sinks[ref.cell->type].count(ref.port); + return tube_clock_sinks.count(ref.cell->type) && tube_clock_sinks.at(ref.cell->type).count(ref.port); } bool NgUltraImpl::is_ring_clock_source(const PortRef &ref) { - return ring_clock_source.count(ref.cell->type) && ring_clock_source[ref.cell->type].count(ref.port); + return ring_clock_source.count(ref.cell->type) && ring_clock_source.at(ref.cell->type).count(ref.port); } bool NgUltraImpl::is_tube_clock_source(const PortRef &ref) { - return tube_clock_source.count(ref.cell->type) && tube_clock_source[ref.cell->type].count(ref.port); + return tube_clock_source.count(ref.cell->type) && tube_clock_source.at(ref.cell->type).count(ref.port); } const NGUltraTileInstExtraDataPOD *NgUltraImpl::tile_extra_data(int tile) const diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.h b/himbaechel/uarch/ng-ultra/ng_ultra.h index e39c3633..33b2af49 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.h +++ b/himbaechel/uarch/ng-ultra/ng_ultra.h @@ -105,14 +105,6 @@ TESTABLE_PRIVATE: bool get_mux_data(WireId wire, uint8_t *value); const NGUltraTileInstExtraDataPOD *tile_extra_data(int tile) const; - - dict> fabric_clock_sinks; - dict> ring_clock_sinks; - dict> ring_over_tile_clock_sinks; - dict> tube_clock_sinks; - - dict> ring_clock_source; - dict> tube_clock_source; }; NEXTPNR_NAMESPACE_END diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc index 4389f4a0..352f8836 100644 --- a/himbaechel/uarch/ng-ultra/pack.cc +++ b/himbaechel/uarch/ng-ultra/pack.cc @@ -1505,7 +1505,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) // If all in ring and none in fabric no need for WFB if (in_ring && !in_fabric) return; log_info(" Inserting WFB for cell '%s' port '%s'\n", cell->name.c_str(ctx), port.c_str(ctx)); - CellInfo *wfb = create_cell_ptr(id_WFB, ctx->id(std::string(cell->name.c_str(ctx)) + "$" + port.c_str(ctx))); + CellInfo *wfb = create_cell_ptr(id_WFB, ctx->idf("%s$%s", cell->name.c_str(ctx), port.c_str(ctx))); if (in_ring && in_fabric) { // If both in ring and in fabric create new signal wfb->connectPort(id_ZI, net); @@ -1521,7 +1521,7 @@ void NgUltraPacker::insert_wfb(CellInfo *cell, IdString port) // Only in fabric, reconnect wire directly to WFB cell->disconnectPort(port); wfb->connectPort(id_ZO, net); - NetInfo *new_out = ctx->createNet(ctx->id(net->name.str(ctx) + "$" + port.c_str(ctx))); + NetInfo *new_out = ctx->createNet(ctx->idf("%s$%s", net->name.c_str(ctx), port.c_str(ctx))); cell->connectPort(port, new_out); wfb->connectPort(id_ZI, new_out); } @@ -2095,7 +2095,7 @@ void NgUltraPacker::duplicate_gck() gck_cell = driver; log_info(" Assign GCK '%s' to lobe %d\n",gck_cell->name.c_str(ctx), conn.first); } else { - gck_cell = create_cell_ptr(id_GCK, ctx->id(driver->name.str(ctx) + "$gck_"+ std::to_string(conn.first))); + gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$gck_%d", driver->name.c_str(ctx), conn.first)); log_info(" Create GCK '%s' for lobe %d\n",gck_cell->name.c_str(ctx), conn.first); for (auto ¶ms : driver->params) gck_cell->params[params.first] = params.second; @@ -2148,7 +2148,7 @@ void NgUltraPacker::insert_bypass_gck() BelId bel = get_available_gck(conn.first, glb_net, nullptr); log_info(" Create GCK for lobe %d\n",conn.first); - CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->id(glb_net->name.str(ctx) + "$gck_"+ std::to_string(conn.first))); + CellInfo *gck_cell = create_cell_ptr(id_GCK, ctx->idf("%s$gck_%d", glb_net->name.c_str(ctx), conn.first)); gck_cell->params[id_std_mode] = Property("BYPASS"); gck_cell->connectPort(id_SI1, glb_net); NetInfo *new_clk = ctx->createNet(ctx->id(gck_cell->name.str(ctx)));