cyclonev: Preparations for validity checking

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-05-03 18:54:31 +01:00
parent 24af19b58d
commit 9bd7ef5f5f
2 changed files with 37 additions and 0 deletions

View File

@ -336,6 +336,12 @@ struct Arch : BaseArch<ArchRanges>
// -------------------------------------------------
bool is_comb_cell(IdString cell_type) const;
bool is_alm_legal(uint32_t lab, uint8_t alm) const;
bool is_lab_ctrlset_legal(uint32_t lab) const;
// -------------------------------------------------
static const std::string defaultPlacer;
static const std::vector<std::string> availablePlacers;
static const std::string defaultRouter;

View File

@ -124,8 +124,39 @@ struct ArchNetInfo
{
};
struct ArchPinInfo
{
// An inverter (INV) has been pushed onto this signal
bool inverted;
// The physical bel pins that this logical pin maps to
std::vector<IdString> bel_pins;
};
struct NetInfo;
struct ArchCellInfo
{
union
{
struct
{
// Store the nets here for fast validity checking (avoids too many map lookups in a hot path)
std::array<const NetInfo *, 7> input_sigs;
const NetInfo *comb_out;
int lut_input_count;
int lut_bits_count;
bool is_carry, is_shared, is_extended;
} combInfo;
struct
{
const NetInfo *clk, *ena, *aclr, *sclr, *sload, *sdata, *datain;
bool clk_inv, ena_inv, aclr_inv, sclr_inv, sload_inv;
} ffInfo;
};
std::unordered_map<IdString, ArchPinInfo> pin_data;
};
NEXTPNR_NAMESPACE_END