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mistral: some more M10K fixes

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This commit is contained in:
Lofty 2022-01-18 12:15:01 +00:00
parent da65afc83b
commit 9be65cd67c
2 changed files with 5 additions and 7 deletions
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4
mistral/bitstream.cc
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@ -126,7 +126,7 @@ struct MistralBitgen
// DATA_FLOW_THRU is probably transparent reads.
cv->bmux_b_set(CycloneV::M10K, pos, CycloneV::A_DATA_FLOW_THRU, bi, 1);
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::A_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_FAST_WRITE, bi, CycloneV::FAST);
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::A_OUTPUT_SEL, bi, CycloneV::REG);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_SA_WREN_DELAY, bi, 1);
@ -135,7 +135,7 @@ struct MistralBitgen
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::A_WR_TIMER_PULSE, bi, 0x0b);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_DATA_FLOW_THRU, bi, 1);
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->attrs[id_CFG_DBITS].as_int64());
cv->bmux_n_set(CycloneV::M10K, pos, CycloneV::B_DATA_WIDTH, bi, ci->params.at(id_CFG_DBITS).as_int64());
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_FAST_WRITE, bi, CycloneV::FAST);
cv->bmux_m_set(CycloneV::M10K, pos, CycloneV::B_OUTPUT_SEL, bi, CycloneV::REG);
cv->bmux_r_set(CycloneV::M10K, pos, CycloneV::B_SA_WREN_DELAY, bi, 1);

8
mistral/pack.cc
View File

@ -399,9 +399,9 @@ struct MistralPacker
// It *does* generate ACLR[01] but leaves them unconnected if unused.
// Enables.
// RDEN[0] and WREN[1] are left unconnected.
ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("RDEN[1]")};
ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("WREN[0]")};
// RDEN[1] and WREN[0] are left unconnected.
ci->pin_data[ctx->id("A1EN")].bel_pins = {ctx->id("WREN[1]")};
ci->pin_data[ctx->id("B1EN")].bel_pins = {ctx->id("RDEN[0]")};
// Clocks.
ci->pin_data[ctx->id("CLK1")].bel_pins = {ctx->id("CLKIN[0]")};
@ -451,8 +451,6 @@ struct MistralPacker
}
for (int bit = 0; bit < dbits; bit++) {
for (int offset : offsets) {
log_info("%s %s\n", ctx->nameOf(ctx->id(stringf("A1DATA[%d]", bit))),
ctx->nameOf(ctx->id(stringf("DATAAIN[%d]", bit + offset))));
ci->pin_data[ctx->id(stringf("A1DATA[%d]", bit))].bel_pins.push_back(
ctx->id(stringf("DATAAIN[%d]", bit + offset)));
}