Gowin. FFs placement. (#1386)
* Gowin. FFs placement. * Allow clusters to be created from FFs and LUTs; * Immediately create pass-through LUTs from free LUTs adjacent to FF - at the same time ensure alternating use of LUT inputs; * In case of constant networks, such pass-through LUTs are disconnected from networks altogether; * Allow FF to be placed directly into SSRAM slides - this is useful when using synchronous reading. Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Fix aux name creation Signed-off-by: YRabbit <rabbit@yrabbit.cyou> * Gowin. Use I3 for pass-trough LUTs Signed-off-by: YRabbit <rabbit@yrabbit.cyou> --------- Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
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@ -71,6 +71,9 @@ struct GowinImpl : HimbaechelAPI
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std::vector<GowinCellInfo> fast_cell_info;
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void assign_cell_info();
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// If there is an unused LUT adjacent to FF, use it
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void create_passthrough_luts(void);
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// Remember HCLK sections that have been reserved to route HCLK signals
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std::set<BelId> routing_reserved_hclk_sections;
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@ -531,6 +534,7 @@ void GowinImpl::postPlace()
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// adjust cell pin to bel pin mapping for DSP cells (CE, CLK and RESET pins)
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adjust_dsp_pin_mapping();
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create_passthrough_luts();
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}
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void GowinImpl::preRoute() { gowin_route_globals(ctx); }
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@ -590,8 +594,15 @@ bool GowinImpl::isBelLocationValid(BelId bel, bool explain_invalid) const
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case ID_ALU:
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return slice_valid(l.x, l.y, l.z - BelZ::ALU0_Z);
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case ID_RAM16SDP4:
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// only slices 4 and 5 are critical for RAM
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return slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 5) && slice_valid(l.x, l.y, l.z - BelZ::RAMW_Z + 4);
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return slice_valid(l.x, l.y, 0);
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case ID_MUX2_LUT5:
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return slice_valid(l.x, l.y, (l.z - BelZ::MUX20_Z) / 2);
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case ID_MUX2_LUT6:
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return slice_valid(l.x, l.y, (l.z - BelZ::MUX21_Z) / 2 + 1);
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case ID_MUX2_LUT7:
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return slice_valid(l.x, l.y, 3);
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case ID_MUX2_LUT8:
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return slice_valid(l.x, l.y, 7);
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case ID_PADD9: /* fall-through */
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case ID_PADD18: /* fall-through */
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case ID_MULT9X9: /* fall-through */
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@ -725,6 +736,67 @@ void GowinImpl::assign_cell_info()
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}
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}
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// If there is an unused LUT next to the DFF, use its inputs for the D input
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void GowinImpl::create_passthrough_luts(void)
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{
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std::vector<std::unique_ptr<CellInfo>> new_cells;
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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if (is_dff(ci)) {
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Loc loc = ctx->getBelLocation(ci->bel);
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BelId lut_bel = ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z - 1));
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CellInfo *lut = ctx->getBoundBelCell(lut_bel);
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CellInfo *alu = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, loc.z / 2 + BelZ::ALU0_Z)));
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const CellInfo *ramw = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(loc.x, loc.y, BelZ::RAMW_Z)));
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if (!(lut || alu || ramw)) {
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if (ctx->debug) {
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log_info("Found an unused LUT:%s, ", ctx->nameOfBel(lut_bel));
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}
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// make LUT
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auto lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_passthrough_lut$"), id_LUT4);
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CellInfo *lut = lut_cell.get();
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NetInfo *d_net = ci->getPort(id_D);
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NPNR_ASSERT(d_net != nullptr);
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if (d_net->name == ctx->id("$PACKER_GND") || d_net->name == ctx->id("$PACKER_VCC")) {
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if (ctx->debug) {
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log("make a constant %s.\n", d_net->name == ctx->id("$PACKER_VCC") ? "VCC" : "GND");
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}
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ci->disconnectPort(id_D);
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if (d_net->name == ctx->id("$PACKER_GND")) {
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lut->setParam(id_INIT, 0x0000);
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} else {
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lut->setParam(id_INIT, 0xffff);
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}
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} else {
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if (ctx->debug) {
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log("make a pass-through.\n");
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}
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IdString lut_input = id_I3;
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int lut_init = 0xff00;
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lut->addInput(lut_input);
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lut->cell_bel_pins[lut_input].clear();
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lut->cell_bel_pins.at(lut_input).push_back(lut_input);
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ci->movePortTo(id_D, lut, lut_input);
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lut->setParam(id_INIT, lut_init);
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}
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lut->addOutput(id_F);
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lut->cell_bel_pins[id_F].clear();
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lut->cell_bel_pins.at(id_F).push_back(id_F);
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ci->connectPorts(id_D, lut, id_F);
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ctx->bindBel(lut_bel, lut, PlaceStrength::STRENGTH_LOCKED);
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new_cells.push_back(std::move(lut_cell));
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}
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}
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}
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for (auto &cell : new_cells) {
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ctx->cells[cell->name] = std::move(cell);
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}
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}
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// DFFs must be same type or compatible
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inline bool incompatible_ffs(const CellInfo *ff, const CellInfo *adj_ff)
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{
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@ -798,22 +870,30 @@ bool GowinImpl::dsp_valid(Loc l, IdString bel_type, bool explain_invalid) const
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bool GowinImpl::slice_valid(int x, int y, int z) const
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{
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const CellInfo *lut = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2)));
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const bool lut_in_4_5 = lut && (z == 4 || z == 5);
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const CellInfo *ff = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z * 2 + 1)));
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// There are only 6 ALUs
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const CellInfo *alu = (z < 6) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, z + BelZ::ALU0_Z))) : nullptr;
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const CellInfo *ramw =
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(z == 4 || z == 5) ? ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z))) : nullptr;
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const CellInfo *ramw = ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, BelZ::RAMW_Z)));
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if (alu && lut) {
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return false;
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}
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if (ramw) {
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if (alu || ff || lut_in_4_5) {
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// FFs in slices 4 and 5 are not allowed
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if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, 4 * 2 + 1))) ||
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ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, 5 * 2 + 1)))) {
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return false;
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}
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return true;
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// ALU/LUTs in slices 4, 5, 6, 7 are not allowed
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for (int i = 4; i < 8; ++i) {
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if (ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, i * 2)))) {
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return false;
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}
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if (i < 6 && ctx->getBoundBelCell(ctx->getBelByLocation(Loc(x, y, i + BelZ::ALU0_Z)))) {
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return false;
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}
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}
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}
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// check for ALU/LUT in the adjacent cell
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@ -829,18 +909,19 @@ bool GowinImpl::slice_valid(int x, int y, int z) const
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return false;
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}
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// if there is DFF it must be connected to this LUT or ALU
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if (ff) {
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static std::vector<int> mux_z = {BelZ::MUX20_Z, BelZ::MUX21_Z, BelZ::MUX20_Z + 4, BelZ::MUX23_Z,
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BelZ::MUX20_Z + 8, BelZ::MUX21_Z + 8, BelZ::MUX20_Z + 12, BelZ::MUX27_Z};
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const auto &ff_data = fast_cell_info.at(ff->flat_index);
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if (lut) {
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const auto &lut_data = fast_cell_info.at(lut->flat_index);
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if (ff_data.ff_d != lut_data.lut_f) {
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return false;
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const NetInfo *src;
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// check implcit LUT(ALU) -> FF connection
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if (lut || alu) {
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if (lut) {
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src = fast_cell_info.at(lut->flat_index).lut_f;
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} else {
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src = fast_cell_info.at(alu->flat_index).alu_sum;
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}
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}
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if (alu) {
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const auto &alu_data = fast_cell_info.at(alu->flat_index);
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if (ff_data.ff_d != alu_data.alu_sum) {
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if (ff_data.ff_d != src) {
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return false;
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}
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}
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@ -817,11 +817,12 @@ def create_logic_tiletype(chip: Chip, db: chipdb, x: int, y: int, ttyp: int, tde
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tt.add_bel_pin(lut, f"I{j}", f"{inp_name}{i}", PinType.INPUT)
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tt.add_bel_pin(lut, "F", f"F{i}", PinType.OUTPUT)
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if i < 6:
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# FF data can come from LUT output, but we pretend that we can use
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# any LUT input
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tt.create_pip(f"F{i}", f"XD{i}", get_tm_class(db, f"F{i}"))
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for inp_name in lut_inputs:
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tt.create_pip(f"{inp_name}{i}", f"XD{i}", get_tm_class(db, f"{inp_name}{i}"))
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# also experimental input for FF using SEL wire - this theory will
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# allow to place unrelated LUT and FF next to each other
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# don't create for now
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#tt.create_pip(f"SEL{i}", f"XD{i}", get_tm_class(db, f"SEL{i}"))
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# FF
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ff = tt.create_bel(f"DFF{i}", "DFF", z =(i * 2 + 1))
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tt.add_bel_pin(ff, "D", f"XD{i}", PinType.INPUT)
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@ -181,6 +181,12 @@ bool GowinUtils::need_BLKSEL_fix(void)
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return extra->chip_flags & Extra_chip_data_POD::NEED_BLKSEL_FIX;
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}
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IdString GowinUtils::create_aux_name(IdString main_name, int idx, const char *str_suffix)
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{
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return idx ? ctx->idf("%s%s%d", main_name.c_str(ctx), str_suffix, idx)
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: ctx->idf("%s%s", main_name.c_str(ctx), str_suffix);
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}
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std::unique_ptr<CellInfo> GowinUtils::create_cell(IdString name, IdString type)
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{
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NPNR_ASSERT(!ctx->cells.count(name));
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@ -107,6 +107,9 @@ struct GowinUtils
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return is_global_wire(ctx->getPipSrcWire(pip)) || is_global_wire(ctx->getPipDstWire(pip));
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}
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// construct name
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IdString create_aux_name(IdString main_name, int idx = 0, const char *str_suffix = "_aux$");
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// make cell but do not include it in the list of chip cells.
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std::unique_ptr<CellInfo> create_cell(IdString name, IdString type);
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@ -508,15 +508,6 @@ struct GowinPacker
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make_iob_nets(*out_iob);
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}
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IdString create_aux_name(IdString main_name, int idx = 0, const char *str_suffix = "_aux$")
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{
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std::string sfx("");
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if (idx) {
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sfx = std::to_string(idx);
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}
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return ctx->id(main_name.str(ctx) + std::string(str_suffix) + sfx);
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}
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BelId get_aux_iologic_bel(const CellInfo &ci)
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{
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return ctx->getBelByLocation(gwu.get_pair_iologic_bel(ctx->getBelLocation(ci.bel)));
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@ -529,7 +520,7 @@ struct GowinPacker
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if (ci.type.in(id_ODDR, id_ODDRC, id_OSER4, id_IDDR, id_IDDRC, id_IDES4)) {
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return nullptr;
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}
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IdString aux_name = create_aux_name(ci.name, idx);
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IdString aux_name = gwu.create_aux_name(ci.name, idx);
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BelId bel = get_aux_iologic_bel(ci);
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BelId io_bel = gwu.get_io_bel_from_iologic(bel);
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if (!ctx->checkBelAvail(io_bel)) {
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@ -720,9 +711,9 @@ struct GowinPacker
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// to simplify packaging, the parts of the OSER16 are presented as IOLOGIC cells
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// and one of these aux cells is declared as main
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IdString main_name = create_aux_name(ci.name);
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IdString main_name = gwu.create_aux_name(ci.name);
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IdString aux_name = create_aux_name(ci.name, 1);
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IdString aux_name = gwu.create_aux_name(ci.name, 1);
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ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
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CellInfo *aux = ctx->cells.at(aux_name).get();
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@ -794,9 +785,9 @@ struct GowinPacker
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// to simplify packaging, the parts of the IDES16 are presented as IOLOGIC cells
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// and one of these aux cells is declared as main
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IdString main_name = create_aux_name(ci.name);
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IdString main_name = gwu.create_aux_name(ci.name);
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IdString aux_name = create_aux_name(ci.name, 1);
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IdString aux_name = gwu.create_aux_name(ci.name, 1);
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ctx->createCell(aux_name, id_IOLOGIC_DUMMY);
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CellInfo *aux = ctx->cells.at(aux_name).get();
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@ -1229,7 +1220,7 @@ struct GowinPacker
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{id_DFFP, id_D}, {id_DFFPE, id_D}, {id_DFFNP, id_D}, {id_DFFNPE, id_D},
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{id_DFFC, id_D}, {id_DFFCE, id_D}, {id_DFFNC, id_D}, {id_DFFNCE, id_D}};
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int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 0);
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int lutffs = h.constrain_cell_pairs(lut_outs, dff_ins, 1, 1);
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log_info("Constrained %d LUTFF pairs.\n", lutffs);
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}
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@ -1365,7 +1356,7 @@ struct GowinPacker
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}
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// Make a decoder
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auto lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_blksel_lut$"), id_LUT4);
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auto lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_blksel_lut$"), id_LUT4);
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CellInfo *lut = lut_cell.get();
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lut->addInput(id_I3);
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ci->movePortTo(id_CE, lut, id_I3);
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@ -1441,7 +1432,7 @@ struct GowinPacker
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}
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// create DFF
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auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), dff_type);
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auto cache_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_dff$"), dff_type);
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CellInfo *cache_dff = cache_dff_cell.get();
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cache_dff->addInput(id_CE);
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cache_dff->connectPort(id_CE, oce_net);
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@ -1477,7 +1468,7 @@ struct GowinPacker
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log_info(" apply the SP fix\n");
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}
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// create WRE LUT
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auto wre_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
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auto wre_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_wre_lut$"), id_LUT4);
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CellInfo *wre_lut = wre_lut_cell.get();
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wre_lut->setParam(id_INIT, 0x8888);
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ci->movePortTo(id_CE, wre_lut, id_I0);
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@ -1486,7 +1477,7 @@ struct GowinPacker
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ci->connectPorts(id_WRE, wre_lut, id_F);
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// create CE LUT
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auto ce_lut_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_lut$"), id_LUT4);
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auto ce_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_lut$"), id_LUT4);
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CellInfo *ce_lut = ce_lut_cell.get();
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ce_lut->setParam(id_INIT, 0xeeee);
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wre_lut->copyPortTo(id_I0, ce_lut, id_I0);
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@ -1497,7 +1488,7 @@ struct GowinPacker
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// create ce reg
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int write_mode = ci->params.at(id_WRITE_MODE).as_int64();
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IdString dff_type = write_mode ? id_DFF : id_DFFR;
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auto ce_pre_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pre_dff$"), dff_type);
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auto ce_pre_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_pre_dff$"), dff_type);
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CellInfo *ce_pre_dff = ce_pre_dff_cell.get();
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ce_pre_dff->addInput(id_D);
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ce_lut->copyPortTo(id_I0, ce_pre_dff, id_D);
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@ -1513,7 +1504,7 @@ struct GowinPacker
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// add delay register in pipeline mode
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int read_mode = ci->params.at(id_READ_MODE).as_int64();
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if (read_mode) {
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auto ce_pipe_dff_cell = gwu.create_cell(create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
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auto ce_pipe_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, 0, "_ce_pipe_dff$"), id_DFF);
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new_cells.push_back(std::move(ce_pipe_dff_cell));
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CellInfo *ce_pipe_dff = new_cells.back().get();
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ce_pipe_dff->addInput(id_D);
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@ -1533,7 +1524,7 @@ struct GowinPacker
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continue;
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}
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// create cache lut
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auto cache_lut_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_lut$"), id_LUT4);
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auto cache_lut_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_lut$"), id_LUT4);
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CellInfo *cache_lut = cache_lut_cell.get();
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cache_lut->setParam(id_INIT, 0xcaca);
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cache_lut->addInput(id_I0);
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@ -1544,7 +1535,7 @@ struct GowinPacker
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new_ce_net_src->connectPorts(id_Q, cache_lut, id_I2);
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// create cache DFF
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auto cache_dff_cell = gwu.create_cell(create_aux_name(ci->name, i, "_cache_dff$"), id_DFFE);
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auto cache_dff_cell = gwu.create_cell(gwu.create_aux_name(ci->name, i, "_cache_dff$"), id_DFFE);
|
||||
CellInfo *cache_dff = cache_dff_cell.get();
|
||||
cache_dff->addInput(id_CE);
|
||||
cache_dff->addInput(id_D);
|
||||
@ -1950,7 +1941,7 @@ struct GowinPacker
|
||||
ci->constr_y = 0;
|
||||
ci->constr_y = 0;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2009,7 +2000,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2020,7 +2011,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::PADD18_0_0_Z + i;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2061,7 +2052,7 @@ struct GowinPacker
|
||||
ci->constr_z = 0;
|
||||
ci->constr_children.clear();
|
||||
|
||||
IdString padd_name = create_aux_name(ci->name);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2103,7 +2094,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2114,7 +2105,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULT18X18_0_0_Z + i;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2161,7 +2152,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 4; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2172,7 +2163,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::ALU54D_0_Z + 4 * (i / 2) + (i % 2);
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2266,7 +2257,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2277,7 +2268,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU18X18_0_Z + i;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2369,7 +2360,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2380,7 +2371,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTALU36X18_0_Z + i;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2463,7 +2454,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 2; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2474,7 +2465,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = BelZ::PADD9_0_0_Z - BelZ::MULTADDALU18X18_0_Z + i;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -2549,7 +2540,7 @@ struct GowinPacker
|
||||
ci->constr_children.clear();
|
||||
|
||||
for (int i = 0; i < 8; ++i) {
|
||||
IdString padd_name = create_aux_name(ci->name, i * 2);
|
||||
IdString padd_name = gwu.create_aux_name(ci->name, i * 2);
|
||||
std::unique_ptr<CellInfo> padd_cell = gwu.create_cell(padd_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(padd_cell));
|
||||
CellInfo *padd_ci = new_cells.back().get();
|
||||
@ -2562,7 +2553,7 @@ struct GowinPacker
|
||||
padd_ci->constr_y = 0;
|
||||
padd_ci->constr_z = padd_z[i / 2] - BelZ::MULT36X36_Z + i % 2;
|
||||
|
||||
IdString mult_name = create_aux_name(ci->name, i * 2 + 1);
|
||||
IdString mult_name = gwu.create_aux_name(ci->name, i * 2 + 1);
|
||||
std::unique_ptr<CellInfo> mult_cell = gwu.create_cell(mult_name, id_DUMMY_CELL);
|
||||
new_cells.push_back(std::move(mult_cell));
|
||||
CellInfo *mult_ci = new_cells.back().get();
|
||||
@ -3165,7 +3156,7 @@ struct GowinPacker
|
||||
}
|
||||
|
||||
std::unique_ptr<CellInfo> lut_cell =
|
||||
gwu.create_cell(create_aux_name(ci.name, lut_idx, "_lut$"), id_LUT4);
|
||||
gwu.create_cell(gwu.create_aux_name(ci.name, lut_idx, "_lut$"), id_LUT4);
|
||||
new_cells.push_back(std::move(lut_cell));
|
||||
CellInfo *lut = new_cells.back().get();
|
||||
lut->addInput(id_I0);
|
||||
@ -3340,8 +3331,7 @@ struct GowinPacker
|
||||
pack_alus();
|
||||
ctx->check();
|
||||
|
||||
// XXX Leads to the impossibility of placement on lower models.
|
||||
// constrain_lutffs();
|
||||
constrain_lutffs();
|
||||
ctx->check();
|
||||
|
||||
pack_pll();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user