machxo2: Detect LOC attributes during packing to implement rudimentary user constraints.
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8417470276
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9c37aef499
@ -262,6 +262,21 @@ std::vector<IdString> Arch::getBelPins(BelId bel) const
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// ---------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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for (int i = 0; i < package_info->num_pins; i++) {
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if (package_info->pin_data[i].name.get() == pin) {
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BelId bel;
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bel.location = package_info->pin_data[i].abs_loc;
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bel.index = package_info->pin_data[i].bel_index;
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return bel;
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}
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}
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return BelId();
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}
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// ---------------------------------------------------------------
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WireId Arch::getWireByName(IdString name) const { return WireId(); }
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IdString Arch::getWireName(WireId wire) const { return IdString(); }
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@ -606,6 +606,9 @@ struct Arch : BaseCtx
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PortType getBelPinType(BelId bel, IdString pin) const;
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std::vector<IdString> getBelPins(BelId bel) const;
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// Package
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BelId getPackagePinBel(const std::string &pin) const;
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// Wires
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WireId getWireByName(IdString name) const;
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IdString getWireName(WireId wire) const;
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@ -175,6 +175,49 @@ static void pack_io(Context *ctx)
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for (auto &p : ci->ports)
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disconnect_port(ctx, ci, p.first);
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packed_cells.insert(ci->name);
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} else if(is_facade_iob(ctx, ci)) {
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// If net attached to PAD port of FACADE_IO has a LOC attribute OR
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// FACADE_IO has LOC attribute, convert the LOC (pin) to a BEL
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// attribute and place FACADE_IO at resulting BEL location.
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auto pad_net = ci->ports[id_PAD].net;
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auto loc_attr_pad = pad_net->attrs.find(ctx->id("LOC"));
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auto loc_attr_cell = ci->attrs.find(ctx->id("LOC"));
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auto bel_attr_cell = ci->attrs.find(ctx->id("BEL"));
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// Handle errors
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if(loc_attr_pad != pad_net->attrs.end() && loc_attr_cell != ci->attrs.end())
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log_error("IO buffer %s and attached PAD net %s both have LOC attributes.\n",
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ci->name.c_str(ctx), pad_net->name.c_str(ctx));
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else if(loc_attr_pad != pad_net->attrs.end() && bel_attr_cell != ci->attrs.end())
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log_error("IO buffer %s has a BEL attribute and attached PAD net %s has a LOC attribute.\n",
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ci->name.c_str(ctx), pad_net->name.c_str(ctx));
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else if(loc_attr_cell != ci->attrs.end() && bel_attr_cell != ci->attrs.end())
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log_error("IO buffer %s has both a BEL attribute and LOC attribute.\n",
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ci->name.c_str(ctx));
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std::string pin;
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// At this point only PAD net or FACADE_IO has LOC attribute.
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if(loc_attr_pad != pad_net->attrs.end()) {
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pin = loc_attr_pad->second.as_string();
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log_info("found LOC attribute on net %s. Will constrain IO buffer %s.\n",
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pad_net->name.c_str(ctx), ci->name.c_str(ctx));
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} else if(loc_attr_cell != ci->attrs.end()) {
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log_info("found LOC attribute on IO buffer %s.\n", ci->name.c_str(ctx));
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pin = loc_attr_cell->second.as_string();
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} else
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// Nothing to do if no LOC attrs.
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continue;
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BelId pinBel = ctx->getPackagePinBel(pin);
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if (pinBel == BelId()) {
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log_error("IO buffer '%s' constrained to pin '%s', which does not exist for package '%s'.\n",
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ci->name.c_str(ctx), pin.c_str(), ctx->args.package.c_str());
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} else {
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log_info("pin '%s' constrained to Bel '%s'.\n", ci->name.c_str(ctx),
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ctx->getBelName(pinBel).c_str(ctx));
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}
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ci->attrs[ctx->id("BEL")] = ctx->getBelName(pinBel).str(ctx);
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}
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}
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