Himbaechel xilinx : DSP packing : Emit a non-fatal error message
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2031a067a0
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@ -210,7 +210,7 @@ struct XC7Packer : public XilinxPacker
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void pack_dsps();
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private:
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void walk_dsp(CellInfo *root, CellInfo *ci, int constr_z);
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unsigned walk_dsp(CellInfo *root, CellInfo *ci, int constr_z);
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void check_valid_pad(CellInfo *ci, std::string type);
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};
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@ -39,9 +39,11 @@ static bool is_cascade_output(const PortInfo& port, const Context *ctx)
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return boost::starts_with(str, "ACOUT") || boost::starts_with(str, "BCOUT") || boost::starts_with(str, "PCOUT");
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}
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void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
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// Return : the number of DSP marked as cascaded
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unsigned XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
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{
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CellInfo *cascaded_cell = nullptr;
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unsigned num_casc = 0;
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auto check_illegal_fanout = [&] (NetInfo *ni, std::string port) {
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if (ni->users.entries() > 1)
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@ -75,21 +77,28 @@ void XC7Packer::walk_dsp(CellInfo *root, CellInfo *current_cell, int constr_z)
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if (cascaded_cell != nullptr) {
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auto is_lower_bel = constr_z == BEL_LOWER_DSP;
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// Creating placement clusters is currently disabled, because the current constraints
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// on Y coordinates don't always correspond to placement possibilities, which makes placer crash
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// Explanation : the current offset +/-5 applies to DSP tiles, not to DSP slices
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// But two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
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#if 0
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cascaded_cell->cluster = root->name;
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root->constr_children.push_back(cascaded_cell);
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cascaded_cell->constr_x = 0;
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// the connected cell has to be above the current cell,
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// otherwise it cannot be routed, because the cascading ports
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// are only connected to the DSP above
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// FIXME The offset +/-5 applies to DSP tiles, not to DSP slices
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// So two cascaded DSPs can be placed in one tile, which does not correspond to a +/-5 offset
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auto previous_y = (current_cell == root) ? 0 : current_cell->constr_y;
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cascaded_cell->constr_y = previous_y + (is_lower_bel ? -5 : 0);
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cascaded_cell->constr_z = constr_z;
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cascaded_cell->constr_abs_z = true;
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#endif
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walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
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num_casc += 1;
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num_casc += walk_dsp(root, cascaded_cell, is_lower_bel ? BEL_UPPER_DSP : BEL_LOWER_DSP);
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}
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return num_casc;
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}
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void XC7Packer::pack_dsps()
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@ -102,6 +111,7 @@ void XC7Packer::pack_dsps()
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std::vector<CellInfo *> all_dsps;
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// Clean connections of DSPs
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for (auto &cell : ctx->cells) {
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CellInfo *ci = cell.second.get();
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@ -155,6 +165,7 @@ void XC7Packer::pack_dsps()
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}
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}
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// Find the roots of cascaded DSP
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std::vector<CellInfo *> dsp_roots;
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for (auto ci : all_dsps) {
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bool cascade_input_used = false;
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@ -171,15 +182,17 @@ void XC7Packer::pack_dsps()
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}
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}
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// Creating placement clusters is currently disabled, because the current constraints
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// on Y coordinates don't always correspond to placement possibilities, which makes placer crash
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#if 0
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// Create clusters of cascaded DSPs
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unsigned num_casc = 0;
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for (auto root : dsp_roots) {
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root->constr_abs_z = true;
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root->constr_z = BEL_LOWER_DSP;
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walk_dsp(root, root, BEL_UPPER_DSP);
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num_casc += walk_dsp(root, root, BEL_UPPER_DSP);
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}
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if(num_casc > 0) {
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log_info("Found %u cascaded DSP from %u roots\n", num_casc, (unsigned)dsp_roots.size());
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log_nonfatal_error("Cascaded DSP are currently not supported by the placer, the design will probably not be functional\n");
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}
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#endif
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}
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NEXTPNR_NAMESPACE_END
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