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Remove separate route lowskew

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This commit is contained in:
Miodrag Milanovic 2024-08-15 08:50:33 +02:00
parent 7134285fbd
commit 9dad56c2c4
3 changed files with 1 additions and 78 deletions
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9
himbaechel/uarch/ng-ultra/ng_ultra.cc
View File

@ -251,13 +251,6 @@ TileTypeExtra NgUltraImpl::tile_type(int tile) const
return (TileTypeExtra)data.tile_type;
}
void NgUltraImpl::preRoute()
{
log_break();
route_lowskew();
log_break();
}
bool NgUltraImpl::get_mux_data(BelId bel, IdString port, uint8_t *value)
{
return get_mux_data(ctx->getBelPinWire(bel, port), value);
@ -817,7 +810,7 @@ void NgUltraImpl::fixup_crossbars()
}
NPNR_ASSERT(found_pip != PipId());
// rebind
log_info(" replacing crossbar pip %s with %s on %s\n", ctx->nameOfPip(pip), ctx->nameOfPip(found_pip), ctx->nameOf(ni));
//log_info(" replacing crossbar pip %s with %s on %s\n", ctx->nameOfPip(pip), ctx->nameOfPip(found_pip), ctx->nameOf(ni));
ctx->bindPip(found_pip, ni, STRENGTH_STRONG);
}
}

2
himbaechel/uarch/ng-ultra/ng_ultra.h
View File

@ -52,7 +52,6 @@ struct NgUltraImpl : HimbaechelAPI
// Flow management
void pack() override;
void postPlace() override;
void preRoute() override;
void postRoute() override;
void configurePlacerHeap(PlacerHeapCfg &cfg) override;
@ -99,7 +98,6 @@ public:
TESTABLE_PRIVATE:
void write_bitstream_json(const std::string &filename);
void route_lowskew();
void parse_csv(const std::string &filename);
void remove_constants();
bool update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip);

68
himbaechel/uarch/ng-ultra/pack.cc
View File

@ -2487,72 +2487,4 @@ void NgUltraPacker::insert_bypass_gck()
}
}
}
void NgUltraImpl::route_lowskew()
{
log_info("Routing lowskew nets...\n");
for (auto &net : ctx->nets) {
NetInfo *glb_net = net.second.get();
if (!glb_net->driver.cell)
continue;
// check if we have a lowskew net, skip otherwise
if (!(is_ring_clock_source(glb_net->driver) || is_tube_clock_source(glb_net->driver)))
continue;
log_info(" routing net '%s'\n", glb_net->name.c_str(ctx));
ctx->bindWire(ctx->getNetinfoSourceWire(glb_net), glb_net, STRENGTH_LOCKED);
for (auto &usr : glb_net->users) {
std::queue<WireId> visit;
dict<WireId, PipId> backtrace;
WireId dest = WireId();
// skip nets that are not part of lowskew routing
if (!(is_fabric_lowskew_sink(usr) || is_tube_clock_sink(usr) || is_ring_over_tile_clock_sink(usr)))
continue;
auto sink_wire = ctx->getNetinfoSinkWire(glb_net, usr, 0);
if (ctx->debug) {
auto sink_wire_name = "(uninitialized)";
if (sink_wire != WireId())
sink_wire_name = ctx->nameOfWire(sink_wire);
log_info(" routing arc to %s.%s (wire %s):\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx),
sink_wire_name);
}
visit.push(sink_wire);
while (!visit.empty()) {
WireId curr = visit.front();
visit.pop();
if (ctx->getBoundWireNet(curr) == glb_net) {
dest = curr;
break;
}
for (auto uh : ctx->getPipsUphill(curr)) {
if (!ctx->checkPipAvail(uh))
continue;
WireId src = ctx->getPipSrcWire(uh);
if (backtrace.count(src))
continue;
if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != glb_net)
continue;
backtrace[src] = uh;
visit.push(src);
}
}
if (dest == WireId()) {
log_info(" failed to find a route using dedicated resources. %s -> %s\n",glb_net->driver.cell->name.c_str(ctx),usr.cell->name.c_str(ctx));
}
while (backtrace.count(dest)) {
auto uh = backtrace[dest];
dest = ctx->getPipDstWire(uh);
if (ctx->getBoundWireNet(dest) == glb_net) {
NPNR_ASSERT(glb_net->wires.at(dest).pip == uh);
break;
}
if (ctx->debug)
log_info(" bind pip %s --> %s\n", ctx->nameOfPip(uh), ctx->nameOfWire(dest));
ctx->bindPip(uh, glb_net, STRENGTH_LOCKED);
}
}
}
}
NEXTPNR_NAMESPACE_END