diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.cc b/himbaechel/uarch/ng-ultra/ng_ultra.cc index 40936757..af058b7b 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.cc +++ b/himbaechel/uarch/ng-ultra/ng_ultra.cc @@ -251,13 +251,6 @@ TileTypeExtra NgUltraImpl::tile_type(int tile) const return (TileTypeExtra)data.tile_type; } -void NgUltraImpl::preRoute() -{ - log_break(); - route_lowskew(); - log_break(); -} - bool NgUltraImpl::get_mux_data(BelId bel, IdString port, uint8_t *value) { return get_mux_data(ctx->getBelPinWire(bel, port), value); @@ -817,7 +810,7 @@ void NgUltraImpl::fixup_crossbars() } NPNR_ASSERT(found_pip != PipId()); // rebind - log_info(" replacing crossbar pip %s with %s on %s\n", ctx->nameOfPip(pip), ctx->nameOfPip(found_pip), ctx->nameOf(ni)); + //log_info(" replacing crossbar pip %s with %s on %s\n", ctx->nameOfPip(pip), ctx->nameOfPip(found_pip), ctx->nameOf(ni)); ctx->bindPip(found_pip, ni, STRENGTH_STRONG); } } diff --git a/himbaechel/uarch/ng-ultra/ng_ultra.h b/himbaechel/uarch/ng-ultra/ng_ultra.h index 507f7831..98ab80bf 100644 --- a/himbaechel/uarch/ng-ultra/ng_ultra.h +++ b/himbaechel/uarch/ng-ultra/ng_ultra.h @@ -52,7 +52,6 @@ struct NgUltraImpl : HimbaechelAPI // Flow management void pack() override; void postPlace() override; - void preRoute() override; void postRoute() override; void configurePlacerHeap(PlacerHeapCfg &cfg) override; @@ -99,7 +98,6 @@ public: TESTABLE_PRIVATE: void write_bitstream_json(const std::string &filename); - void route_lowskew(); void parse_csv(const std::string &filename); void remove_constants(); bool update_bff_to_csc(CellInfo *cell, BelId bel, PipId dst_pip); diff --git a/himbaechel/uarch/ng-ultra/pack.cc b/himbaechel/uarch/ng-ultra/pack.cc index fc325984..52290290 100644 --- a/himbaechel/uarch/ng-ultra/pack.cc +++ b/himbaechel/uarch/ng-ultra/pack.cc @@ -2487,72 +2487,4 @@ void NgUltraPacker::insert_bypass_gck() } } } -void NgUltraImpl::route_lowskew() -{ - log_info("Routing lowskew nets...\n"); - for (auto &net : ctx->nets) { - NetInfo *glb_net = net.second.get(); - if (!glb_net->driver.cell) - continue; - - // check if we have a lowskew net, skip otherwise - if (!(is_ring_clock_source(glb_net->driver) || is_tube_clock_source(glb_net->driver))) - continue; - - log_info(" routing net '%s'\n", glb_net->name.c_str(ctx)); - ctx->bindWire(ctx->getNetinfoSourceWire(glb_net), glb_net, STRENGTH_LOCKED); - - for (auto &usr : glb_net->users) { - std::queue visit; - dict backtrace; - WireId dest = WireId(); - // skip nets that are not part of lowskew routing - if (!(is_fabric_lowskew_sink(usr) || is_tube_clock_sink(usr) || is_ring_over_tile_clock_sink(usr))) - continue; - - auto sink_wire = ctx->getNetinfoSinkWire(glb_net, usr, 0); - if (ctx->debug) { - auto sink_wire_name = "(uninitialized)"; - if (sink_wire != WireId()) - sink_wire_name = ctx->nameOfWire(sink_wire); - log_info(" routing arc to %s.%s (wire %s):\n", usr.cell->name.c_str(ctx), usr.port.c_str(ctx), - sink_wire_name); - } - visit.push(sink_wire); - while (!visit.empty()) { - WireId curr = visit.front(); - visit.pop(); - if (ctx->getBoundWireNet(curr) == glb_net) { - dest = curr; - break; - } - for (auto uh : ctx->getPipsUphill(curr)) { - if (!ctx->checkPipAvail(uh)) - continue; - WireId src = ctx->getPipSrcWire(uh); - if (backtrace.count(src)) - continue; - if (!ctx->checkWireAvail(src) && ctx->getBoundWireNet(src) != glb_net) - continue; - backtrace[src] = uh; - visit.push(src); - } - } - if (dest == WireId()) { - log_info(" failed to find a route using dedicated resources. %s -> %s\n",glb_net->driver.cell->name.c_str(ctx),usr.cell->name.c_str(ctx)); - } - while (backtrace.count(dest)) { - auto uh = backtrace[dest]; - dest = ctx->getPipDstWire(uh); - if (ctx->getBoundWireNet(dest) == glb_net) { - NPNR_ASSERT(glb_net->wires.at(dest).pip == uh); - break; - } - if (ctx->debug) - log_info(" bind pip %s --> %s\n", ctx->nameOfPip(uh), ctx->nameOfWire(dest)); - ctx->bindPip(uh, glb_net, STRENGTH_LOCKED); - } - } - } -} NEXTPNR_NAMESPACE_END