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ecp5: Split bitstream generation into more functions

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Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2022-09-15 13:28:43 +02:00
parent 79aad0988a
commit 9e272810d8
1 changed files with 1503 additions and 1448 deletions
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587
ecp5/bitstream.cc
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@ -46,8 +46,13 @@ void config_empty_lfe5um5g_45f(ChipConfig &cc);
void config_empty_lfe5um5g_85f(ChipConfig &cc); void config_empty_lfe5um5g_85f(ChipConfig &cc);
} // namespace BaseConfigs } // namespace BaseConfigs
// Convert an absolute wire name to a relative Trellis one namespace {
static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire) struct ECP5Bitgen
{
explicit ECP5Bitgen(Context *ctx) : ctx(ctx){};
Context *ctx;
ChipConfig cc;
std::string get_trellis_wirename(Location loc, WireId wire)
{ {
std::string basename = ctx->loc_info(wire)->wire_data[wire.index].name.get(); std::string basename = ctx->loc_info(wire)->wire_data[wire.index].name.get();
std::string prefix2 = basename.substr(0, 2); std::string prefix2 = basename.substr(0, 2);
@ -66,8 +71,7 @@ static std::string get_trellis_wirename(Context *ctx, Location loc, WireId wire)
rel_prefix += "W" + std::to_string(loc.x - wire.location.x); rel_prefix += "W" + std::to_string(loc.x - wire.location.x);
return rel_prefix + "_" + basename; return rel_prefix + "_" + basename;
} }
std::vector<bool> int_to_bitvector(int val, int size)
static std::vector<bool> int_to_bitvector(int val, int size)
{ {
std::vector<bool> bv; std::vector<bool> bv;
for (int i = 0; i < size; i++) { for (int i = 0; i < size; i++) {
@ -75,8 +79,7 @@ static std::vector<bool> int_to_bitvector(int val, int size)
} }
return bv; return bv;
} }
std::vector<bool> str_to_bitvector(std::string str, int size)
static std::vector<bool> str_to_bitvector(std::string str, int size)
{ {
std::vector<bool> bv; std::vector<bool> bv;
bv.resize(size, 0); bv.resize(size, 0);
@ -91,7 +94,7 @@ static std::vector<bool> str_to_bitvector(std::string str, int size)
} }
// Tie a wire using the CIB ties // Tie a wire using the CIB ties
static void tie_cib_signal(Context *ctx, ChipConfig &cc, WireId wire, bool value) void tie_cib_signal(WireId wire, bool value)
{ {
static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]"); static const std::regex cib_re("J([A-D]|CE|LSR|CLK)[0-7]");
std::queue<WireId> signals; std::queue<WireId> signals;
@ -144,8 +147,8 @@ std::vector<bool> parse_init_str(const Property &p, int length, const char *cell
NPNR_ASSERT(str.substr(0, 2) == "0x"); NPNR_ASSERT(str.substr(0, 2) == "0x");
// Lattice style hex string // Lattice style hex string
if (int(str.length()) > (2 + ((length + 3) / 4))) if (int(str.length()) > (2 + ((length + 3) / 4)))
log_error("hex string value too long, expected up to %d chars and found %d.\n", (2 + ((length + 3) / 4)), log_error("hex string value too long, expected up to %d chars and found %d.\n",
int(str.length())); (2 + ((length + 3) / 4)), int(str.length()));
for (int i = 0; i < int(str.length()) - 2; i++) { for (int i = 0; i < int(str.length()) - 2; i++) {
char c = str.at((str.size() - i) - 1); char c = str.at((str.size() - i) - 1);
int nibble = chtohex(c); int nibble = chtohex(c);
@ -176,7 +179,7 @@ inline uint16_t bit_reverse(uint16_t x, int size)
} }
// Get the PIO tile corresponding to a PIO bel // Get the PIO tile corresponding to a PIO bel
static std::string get_pio_tile(Context *ctx, BelId bel) std::string get_pio_tile(BelId bel)
{ {
static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"}; static const std::set<std::string> pioabcd_l = {"PICL1", "PICL1_DQS0", "PICL1_DQS3"};
static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"}; static const std::set<std::string> pioabcd_r = {"PICR1", "PICR1_DQS0", "PICR1_DQS3"};
@ -210,7 +213,7 @@ static std::string get_pio_tile(Context *ctx, BelId bel)
} }
// Get the PIC tile corresponding to a PIO bel // Get the PIC tile corresponding to a PIO bel
static std::string get_pic_tile(Context *ctx, BelId bel) std::string get_pic_tile(BelId bel)
{ {
static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"}; static const std::set<std::string> picab_l = {"PICL0", "PICL0_DQS2"};
static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"}; static const std::set<std::string> piccd_l = {"PICL2", "PICL2_DQS1", "MIB_CIB_LR"};
@ -259,27 +262,27 @@ static std::string get_pic_tile(Context *ctx, BelId bel)
} }
// Get the complement PIC and PIO tiles for a pseudo differential IO // Get the complement PIC and PIO tiles for a pseudo differential IO
static std::string get_comp_pio_tile(Context *ctx, BelId bel) std::string get_comp_pio_tile(BelId bel)
{ {
NPNR_ASSERT(bel.location.y == 0); NPNR_ASSERT(bel.location.y == 0);
return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1"); return ctx->get_tile_by_type_loc(0, bel.location.x + 1, "PIOT1");
} }
static std::string get_comp_pic_tile(Context *ctx, BelId bel) std::string get_comp_pic_tile(BelId bel)
{ {
NPNR_ASSERT(bel.location.y == 0); NPNR_ASSERT(bel.location.y == 0);
return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1"); return ctx->get_tile_by_type_loc(1, bel.location.x + 1, "PICT1");
} }
// Get the list of tiles corresponding to a blockram // Get the list of tiles corresponding to a blockram
std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel) std::vector<std::string> get_bram_tiles(BelId bel)
{ {
std::vector<std::string> tiles; std::vector<std::string> tiles;
Loc loc = ctx->getBelLocation(bel); Loc loc = ctx->getBelLocation(bel);
static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"}; static const std::set<std::string> ebr0 = {"MIB_EBR0", "EBR_CMUX_UR", "EBR_CMUX_LR", "EBR_CMUX_LR_25K"};
static const std::set<std::string> ebr8 = {"MIB_EBR8", "EBR_SPINE_UL1", "EBR_SPINE_UR1", "EBR_SPINE_LL1", static const std::set<std::string> ebr8 = {
"EBR_CMUX_UL", "EBR_SPINE_LL0", "EBR_CMUX_LL", "EBR_SPINE_LR0", "MIB_EBR8", "EBR_SPINE_UL1", "EBR_SPINE_UR1", "EBR_SPINE_LL1", "EBR_CMUX_UL", "EBR_SPINE_LL0",
"EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0", "EBR_CMUX_LL", "EBR_SPINE_LR0", "EBR_SPINE_LR1", "EBR_CMUX_LL_25K", "EBR_SPINE_UL2", "EBR_SPINE_UL0",
"EBR_SPINE_UR2", "EBR_SPINE_LL2", "EBR_SPINE_LR2", "EBR_SPINE_UR0"}; "EBR_SPINE_UR2", "EBR_SPINE_LL2", "EBR_SPINE_LR2", "EBR_SPINE_UR0"};
switch (loc.z) { switch (loc.z) {
@ -309,7 +312,7 @@ std::vector<std::string> get_bram_tiles(Context *ctx, BelId bel)
} }
// Get the list of tiles corresponding to a DSP // Get the list of tiles corresponding to a DSP
std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel) std::vector<std::string> get_dsp_tiles(BelId bel)
{ {
std::vector<std::string> tiles; std::vector<std::string> tiles;
Loc loc = ctx->getBelLocation(bel); Loc loc = ctx->getBelLocation(bel);
@ -402,7 +405,7 @@ std::vector<std::string> get_dsp_tiles(Context *ctx, BelId bel)
} }
// Get the list of tiles corresponding to a DCU // Get the list of tiles corresponding to a DCU
std::vector<std::string> get_dcu_tiles(Context *ctx, BelId bel) std::vector<std::string> get_dcu_tiles(BelId bel)
{ {
std::vector<std::string> tiles; std::vector<std::string> tiles;
Loc loc = ctx->getBelLocation(bel); Loc loc = ctx->getBelLocation(bel);
@ -412,7 +415,7 @@ std::vector<std::string> get_dcu_tiles(Context *ctx, BelId bel)
} }
// Get the list of tiles corresponding to a PLL // Get the list of tiles corresponding to a PLL
std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel) std::vector<std::string> get_pll_tiles(BelId bel)
{ {
std::string name = ctx->loc_info(bel)->bel_data[bel.index].name.get(); std::string name = ctx->loc_info(bel)->bel_data[bel.index].name.get();
std::vector<std::string> tiles; std::vector<std::string> tiles;
@ -437,7 +440,7 @@ std::vector<std::string> get_pll_tiles(Context *ctx, BelId bel)
return tiles; return tiles;
} }
void fix_tile_names(Context *ctx, ChipConfig &cc) void fix_tile_names()
{ {
// Remove the V prefix/suffix on certain tiles if device is a SERDES variant // Remove the V prefix/suffix on certain tiles if device is a SERDES variant
if (ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F || if (ctx->args.type == ArchArgs::LFE5U_12F || ctx->args.type == ArchArgs::LFE5U_25F ||
@ -484,7 +487,7 @@ void fix_tile_names(Context *ctx, ChipConfig &cc)
} }
} }
void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci) void tieoff_dsp_ports(CellInfo *ci)
{ {
for (auto port : ci->ports) { for (auto port : ci->ports) {
if (port.second.net == nullptr && port.second.type == PORT_IN) { if (port.second.net == nullptr && port.second.type == PORT_IN) {
@ -497,12 +500,12 @@ void tieoff_dsp_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
port.first.str(ctx).substr(0, 2) == "OP") port.first.str(ctx).substr(0, 2) == "OP")
continue; continue;
bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false); bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
} }
} }
} }
void tieoff_dcu_ports(Context *ctx, ChipConfig &cc, CellInfo *ci) void tieoff_dcu_ports(CellInfo *ci)
{ {
for (auto port : ci->ports) { for (auto port : ci->ports) {
if (port.second.net == nullptr && port.second.type == PORT_IN) { if (port.second.net == nullptr && port.second.type == PORT_IN) {
@ -511,20 +514,20 @@ void tieoff_dcu_ports(Context *ctx, ChipConfig &cc, CellInfo *ci)
port.first.str(ctx).find("HDOUT") != std::string::npos) port.first.str(ctx).find("HDOUT") != std::string::npos)
continue; continue;
bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false); bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
} }
} }
} }
static void set_pip(Context *ctx, ChipConfig &cc, PipId pip) void set_pip(PipId pip)
{ {
std::string tile = ctx->get_pip_tilename(pip); std::string tile = ctx->get_pip_tilename(pip);
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip)); std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
std::string sink = get_trellis_wirename(ctx, pip.location, ctx->getPipDstWire(pip)); std::string sink = get_trellis_wirename(pip.location, ctx->getPipDstWire(pip));
cc.tiles[tile].add_arc(sink, source); cc.tiles[tile].add_arc(sink, source);
} }
static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init) unsigned permute_lut(CellInfo *cell, pool<IdString> &used_phys_pins, unsigned orig_init)
{ {
std::array<std::vector<unsigned>, 4> phys_to_log; std::array<std::vector<unsigned>, 4> phys_to_log;
const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D}; const std::array<IdString, 4> ports{id_A, id_B, id_C, id_D};
@ -573,7 +576,7 @@ static unsigned permute_lut(Context *ctx, CellInfo *cell, pool<IdString> &used_p
return permuted_init; return permuted_init;
} }
static std::vector<bool> parse_config_str(const Property &p, int length) std::vector<bool> parse_config_str(const Property &p, int length)
{ {
std::vector<bool> word; std::vector<bool> word;
if (p.is_string) { if (p.is_string) {
@ -636,96 +639,10 @@ std::string intstr_or_default(const dict<IdString, Property> &ct, const IdString
} }
}; };
void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
{
ChipConfig cc;
std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
if (!base_config_file.empty()) {
std::ifstream config_file(base_config_file);
if (!config_file) {
log_error("failed to open base config file '%s'\n", base_config_file.c_str());
}
config_file >> cc;
} else {
switch (ctx->args.type) {
case ArchArgs::LFE5U_12F:
BaseConfigs::config_empty_lfe5u_25f(cc);
cc.chip_name = "LFE5U-12F";
break;
case ArchArgs::LFE5U_25F:
BaseConfigs::config_empty_lfe5u_25f(cc);
break;
case ArchArgs::LFE5U_45F:
BaseConfigs::config_empty_lfe5u_45f(cc);
break;
case ArchArgs::LFE5U_85F:
BaseConfigs::config_empty_lfe5u_85f(cc);
break;
case ArchArgs::LFE5UM_25F:
BaseConfigs::config_empty_lfe5um_25f(cc);
break;
case ArchArgs::LFE5UM_45F:
BaseConfigs::config_empty_lfe5um_45f(cc);
break;
case ArchArgs::LFE5UM_85F:
BaseConfigs::config_empty_lfe5um_85f(cc);
break;
case ArchArgs::LFE5UM5G_25F:
BaseConfigs::config_empty_lfe5um5g_25f(cc);
break;
case ArchArgs::LFE5UM5G_45F:
BaseConfigs::config_empty_lfe5um5g_45f(cc);
break;
case ArchArgs::LFE5UM5G_85F:
BaseConfigs::config_empty_lfe5um5g_85f(cc);
break;
default:
NPNR_ASSERT_FALSE("Unsupported device type");
}
}
cc.metadata.push_back("Part: " + ctx->get_full_chip_name());
// Clear out DCU tieoffs in base config if DCU used
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_DCUA) {
Loc loc = ctx->getBelLocation(ci->bel);
for (int i = 0; i < 12; i++) {
auto tiles = ctx->get_tiles_at_loc(loc.y - 1, loc.x + i);
for (const auto &tile : tiles) {
auto cc_tile = cc.tiles.find(tile.first);
if (cc_tile != cc.tiles.end()) {
cc_tile->second.cenums.clear();
cc_tile->second.cunknowns.clear();
}
}
}
}
}
// Add all set, configurable pips to the config
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != nullptr) {
if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
std::string source = get_trellis_wirename(ctx, pip.location, ctx->getPipSrcWire(pip));
if (source.find("CLKI_PLL") != std::string::npos) {
// Special case - must set pip in all relevant tiles
for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
set_pip(ctx, cc, equiv_pip);
}
} else {
set_pip(ctx, cc, pip);
}
}
}
}
// Find bank voltages
dict<int, IOVoltage> bankVcc; dict<int, IOVoltage> bankVcc;
dict<int, bool> bankLvds, bankVref, bankDiff; dict<int, bool> bankLvds, bankVref, bankDiff;
void init_io_banks()
{
for (auto &cell : ctx->cells) { for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get(); CellInfo *ci = cell.second.get();
if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) { if (ci->bel != BelId() && ci->type == id_TRELLIS_IO) {
@ -800,14 +717,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (!ctx->checkBelAvail(vrefIO)) { if (!ctx->checkBelAvail(vrefIO)) {
CellInfo *bound = ctx->getBoundBelCell(vrefIO); CellInfo *bound = ctx->getBoundBelCell(vrefIO);
if (bound != nullptr) if (bound != nullptr)
log_error("VREF pin %s of bank %d is occupied by IO '%s'\n", ctx->get_bel_package_pin(vrefIO).c_str(), log_error("VREF pin %s of bank %d is occupied by IO '%s'\n",
bv.first, bound->name.c_str(ctx)); ctx->get_bel_package_pin(vrefIO).c_str(), bv.first, bound->name.c_str(ctx));
else else
log_error("VREF pin %s of bank %d is unavailable\n", ctx->get_bel_package_pin(vrefIO).c_str(), log_error("VREF pin %s of bank %d is unavailable\n", ctx->get_bel_package_pin(vrefIO).c_str(),
bv.first); bv.first);
} }
log_info("Using pin %s as VREF for bank %d\n", ctx->get_bel_package_pin(vrefIO).c_str(), bv.first); log_info("Using pin %s as VREF for bank %d\n", ctx->get_bel_package_pin(vrefIO).c_str(), bv.first);
std::string pio_tile = get_pio_tile(ctx, vrefIO); std::string pio_tile = get_pio_tile(vrefIO);
std::string iotype; std::string iotype;
switch (bankVcc[bv.first]) { switch (bankVcc[bv.first]) {
@ -832,30 +749,25 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype); cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", "OUTPUT_" + iotype);
cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE"); cc.tiles[pio_tile].add_enum(pio + ".PULLMODE", "NONE");
} }
// Configure slices
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->bel == BelId()) {
log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
} }
BelId bel = ci->bel;
if (ci->type == id_TRELLIS_COMB) { void write_comb(CellInfo *ci)
{
pool<IdString> used_phys_pins; pool<IdString> used_phys_pins;
BelId bel = ci->bel;
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2"); std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift; int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
std::string slice = std::string("SLICE") + "ABCD"[z / 2]; std::string slice = std::string("SLICE") + "ABCD"[z / 2];
std::string lc = std::to_string(z % 2); std::string lc = std::to_string(z % 2);
std::string mode = str_or_default(ci->params, id_MODE, "LOGIC"); std::string mode = str_or_default(ci->params, id_MODE, "LOGIC");
if (mode == "RAMW_BLOCK") if (mode == "RAMW_BLOCK")
continue; return;
int lut_init = int_or_default(ci->params, id_INITVAL); int lut_init = int_or_default(ci->params, id_INITVAL);
cc.tiles[tname].add_enum(slice + ".MODE", mode); cc.tiles[tname].add_enum(slice + ".MODE", mode);
cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT", cc.tiles[tname].add_word(slice + ".K" + lc + ".INIT",
int_to_bitvector(permute_lut(ctx, ci, used_phys_pins, lut_init), 16)); int_to_bitvector(permute_lut(ci, used_phys_pins, lut_init), 16));
if (mode == "CCU2") { if (mode == "CCU2") {
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
str_or_default(ci->params, id_CCU2_INJECT1, "YES"));
} else { } else {
// Don't interfere with cascade mux wiring // Don't interfere with cascade mux wiring
cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_"); cc.tiles[tname].add_enum(slice + ".CCU2.INJECT1_" + lc, "_NONE_");
@ -871,7 +783,11 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + lc + "MUX", "1"); cc.tiles[tname].add_enum(slice + "." + input.str(ctx) + lc + "MUX", "1");
} }
} }
} else if (ci->type == id_TRELLIS_FF) { }
void write_ff(CellInfo *ci)
{
BelId bel = ci->bel;
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2"); std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift; int z = ctx->loc_info(bel)->bel_data[bel.index].z >> Arch::lc_idx_shift;
std::string slice = std::string("SLICE") + "ABCD"[z / 2]; std::string slice = std::string("SLICE") + "ABCD"[z / 2];
@ -901,17 +817,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) { if (ctx->getBoundWireNet(ctx->get_wire_by_loc_basename(bel.location, "CLK1")) == clknet) {
cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK")); cc.tiles[tname].add_enum("CLK1.CLKMUX", str_or_default(ci->params, id_CLKMUX, "CLK"));
} }
} else if (ci->type == id_TRELLIS_RAMW) { }
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW"); std::set<std::string> cib_tiles = {"CIB", "CIB_LR", "CIB_LR_S", "CIB_EFB0", "CIB_EFB1"};
cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false)); void write_io(CellInfo *ci)
} else if (ci->type == id_TRELLIS_IO) { {
BelId bel = ci->bel;
std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get(); std::string pio = ctx->loc_info(bel)->bel_data[bel.index].name.get();
std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33"); std::string iotype = str_or_default(ci->attrs, id_IO_TYPE, "LVCMOS33");
std::string dir = str_or_default(ci->params, id_DIR, "INPUT"); std::string dir = str_or_default(ci->params, id_DIR, "INPUT");
std::string pio_tile = get_pio_tile(ctx, bel); std::string pio_tile = get_pio_tile(bel);
std::string pic_tile = get_pic_tile(ctx, bel); std::string pic_tile = get_pic_tile(bel);
cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[pio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[pic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
if (is_differential(ioType_from_str(iotype))) { if (is_differential(ioType_from_str(iotype))) {
@ -920,10 +837,9 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (dir != "OUTPUT") if (dir != "OUTPUT")
log_error("Pseudo-differential IO '%s' must be output\n", ctx->nameOf(ci)); log_error("Pseudo-differential IO '%s' must be output\n", ctx->nameOf(ci));
if (pio != "PIOA") if (pio != "PIOA")
log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n", log_error("Pseudo-differential IO '%s' must be constrained to 'A' side of pair\n", ctx->nameOf(ci));
ctx->nameOf(ci)); std::string cpio_tile = get_comp_pio_tile(bel);
std::string cpio_tile = get_comp_pio_tile(ctx, bel); std::string cpic_tile = get_comp_pic_tile(bel);
std::string cpic_tile = get_comp_pic_tile(ctx, bel);
cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[cpio_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype); cc.tiles[cpic_tile].add_enum(pio + ".BASE_TYPE", dir + "_" + iotype);
} else { } else {
@ -976,7 +892,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
// Pseudo differential top IO // Pseudo differential top IO
NPNR_ASSERT(dir == "OUTPUT"); NPNR_ASSERT(dir == "OUTPUT");
NPNR_ASSERT(pio == "PIOA"); NPNR_ASSERT(pio == "PIOA");
std::string cpio_tile = get_comp_pio_tile(ctx, bel); std::string cpio_tile = get_comp_pio_tile(bel);
cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12")); cc.tiles[pio_tile].add_enum("PIOA.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12")); cc.tiles[cpio_tile].add_enum("PIOB.DRIVE", str_or_default(ci->attrs, id_DRIVE, "12"));
} else { } else {
@ -1000,20 +916,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
auto vccio = get_vccio(ioType_from_str(iotype)); auto vccio = get_vccio(ioType_from_str(iotype));
switch (vccio) { switch (vccio) {
case IOVoltage::VCC_1V8: case IOVoltage::VCC_1V8:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8", cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V8", str_or_default(ci->attrs, id_TERMINATION, "OFF"));
str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break; break;
case IOVoltage::VCC_1V5: case IOVoltage::VCC_1V5:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5", cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V5", str_or_default(ci->attrs, id_TERMINATION, "OFF"));
str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break; break;
case IOVoltage::VCC_1V35: case IOVoltage::VCC_1V35:
cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35", cc.tiles[pio_tile].add_enum(pio + ".TERMINATION_1V35",
str_or_default(ci->attrs, id_TERMINATION, "OFF")); str_or_default(ci->attrs, id_TERMINATION, "OFF"));
break; break;
default: default:
log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n", log_error("TERMINATION is not supported with Vcc = %s (on PIO %s)\n", iovoltage_to_str(vccio).c_str(),
iovoltage_to_str(vccio).c_str(), ci->name.c_str(ctx)); ci->name.c_str(ctx));
} }
} }
if (ci->attrs.count(id_OPENDRAIN)) { if (ci->attrs.count(id_OPENDRAIN)) {
@ -1042,11 +956,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT"); std::string trimux_tsreg = str_or_default(ci->params, id_TRIMUX_TSREG, "PADDT");
if (trimux_tsreg != "PADDT") if (trimux_tsreg != "PADDT")
cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg); cc.tiles[pic_tile].add_enum(pio + ".TRIMUX_TSREG", trimux_tsreg);
} else if (ci->type == id_DCCA) { }
void write_dcc(CellInfo *ci)
{
const NetInfo *cen = ci->getPort(id_CE); const NetInfo *cen = ci->getPort(id_CE);
if (cen != nullptr) { if (cen != nullptr) {
std::string belname = ctx->loc_info(bel)->bel_data[bel.index].name.get(); std::string belname = ctx->loc_info(ci->bel)->bel_data[ci->bel.index].name.get();
Loc loc = ctx->getBelLocation(bel); Loc loc = ctx->getBelLocation(ci->bel);
TileGroup tg; TileGroup tg;
switch (belname[0]) { switch (belname[0]) {
case 'B': case 'B':
@ -1072,21 +989,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA"); tg.config.add_enum(std::string("DCC_") + belname[0] + belname.substr(4) + ".MODE", "DCCA");
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
} }
} else if (ci->type == id_DCSC) { }
std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles); void write_bram(CellInfo *ci)
std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get(); {
cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
} else if (ci->type == id_DP16KD) {
TileGroup tg; TileGroup tg;
Loc loc = ctx->getBelLocation(ci->bel); Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_bram_tiles(ctx, ci->bel); tg.tiles = get_bram_tiles(ci->bel);
std::string ebr = "EBR" + std::to_string(loc.z); std::string ebr = "EBR" + std::to_string(loc.z);
if (ci->ramInfo.is_pdp) { if (ci->ramInfo.is_pdp) {
tg.config.add_enum(ebr + ".MODE", "PDPW16KD"); tg.config.add_enum(ebr + ".MODE", "PDPW16KD");
tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R", tg.config.add_enum(ebr + ".PDPW16KD.DATA_WIDTH_R", intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
intstr_or_default(ci->params, id_DATA_WIDTH_B, "36"));
} else { } else {
tg.config.add_enum(ebr + ".MODE", "DP16KD"); tg.config.add_enum(ebr + ".MODE", "DP16KD");
tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18")); tg.config.add_enum(ebr + ".DP16KD.DATA_WIDTH_A", intstr_or_default(ci->params, id_DATA_WIDTH_A, "18"));
@ -1102,8 +1016,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG")); tg.config.add_enum(ebr + ".REGMODE_B", str_or_default(ci->params, id_REGMODE_B, "NOREG"));
tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC")); tg.config.add_enum(ebr + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE", tg.config.add_enum(ebr + ".ASYNC_RESET_RELEASE", str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
str_or_default(ci->params, id_ASYNC_RESET_RELEASE, "SYNC"));
tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED")); tg.config.add_enum(ebr + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9)); tg.config.add_word(ebr + ".WID", int_to_bitvector(bit_reverse(int_or_default(ci->attrs, id_WID, 0), 9), 9));
@ -1116,26 +1029,26 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) { if (port.first.in(id_CLKA, id_CLKB, id_WEA, id_WEB, id_RSTA, id_RSTB)) {
// CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB // CIB clock or LSR. Tie to "1" (also 0 in prjtrellis db?) in CIB
// If MUX doesn't exist, set to INV to emulate default 0 // If MUX doesn't exist, set to INV to emulate default 0
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX"))) if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV"); ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
} else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) { } else if (port.first.in(id_CEA, id_CEB, id_OCEA, id_OCEB)) {
// CIB CE. Tie to "1" in CIB // CIB CE. Tie to "1" in CIB
// If MUX doesn't exist, set to passthru to emulate default 1 // If MUX doesn't exist, set to passthru to emulate default 1
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX"))) if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx); ci->params[ctx->id(port.first.str(ctx) + "MUX")] = port.first.str(ctx);
} else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) { } else if (port.first.in(id_CSA0, id_CSA1, id_CSA2, id_CSB0, id_CSB1, id_CSB2)) {
// CIB CE. Tie to "1" in CIB. // CIB CE. Tie to "1" in CIB.
// If MUX doesn't exist, set to INV to emulate default 0 // If MUX doesn't exist, set to INV to emulate default 0
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), true); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), true);
if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX"))) if (!ci->params.count(ctx->id(port.first.str(ctx) + "MUX")))
ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV"); ci->params[ctx->id(port.first.str(ctx) + "MUX")] = std::string("INV");
} else { } else {
// CIB ABCD signal // CIB ABCD signal
// Tie signals low unless explicit MUX param specified // Tie signals low unless explicit MUX param specified
bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false); bool value = bool_or_default(ci->params, ctx->id(port.first.str(ctx) + "MUX"), false);
tie_cib_signal(ctx, cc, ctx->getBelPinWire(ci->bel, port.first), value); tie_cib_signal(ctx->getBelPinWire(ci->bel, port.first), value);
} }
} }
} }
@ -1173,8 +1086,7 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
init_data.resize(2048, 0x0); init_data.resize(2048, 0x0);
// INIT_00 .. INIT_3F // INIT_00 .. INIT_3F
for (int i = 0; i <= 0x3F; i++) { for (int i = 0; i <= 0x3F; i++) {
IdString param = ctx->id("INITVAL_" + IdString param = ctx->idf("INITVAL_%02X", i);
fmt_str(std::hex << std::uppercase << std::setw(2) << std::setfill('0') << i));
auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx)); auto value = parse_init_str(get_or_default(ci->params, param, Property(0)), 320, ci->name.c_str(ctx));
for (int j = 0; j < 16; j++) { for (int j = 0; j < 16; j++) {
// INIT parameter consists of 16 18-bit words with 2-bit padding // INIT parameter consists of 16 18-bit words with 2-bit padding
@ -1189,10 +1101,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
NPNR_ASSERT(!cc.bram_data.count(wid)); NPNR_ASSERT(!cc.bram_data.count(wid));
cc.bram_data[wid] = init_data; cc.bram_data[wid] = init_data;
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
} else if (ci->type == id_MULT18X18D) { }
void write_mult18(CellInfo *ci)
{
TileGroup tg; TileGroup tg;
Loc loc = ctx->getBelLocation(ci->bel); Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_dsp_tiles(ctx, ci->bel); tg.tiles = get_dsp_tiles(ci->bel);
std::string dsp = "MULT18_" + std::to_string(loc.z); std::string dsp = "MULT18_" + std::to_string(loc.z);
tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_INPUTA_CLK", str_or_default(ci->params, id_REG_INPUTA_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0")); tg.config.add_enum(dsp + ".REG_INPUTA_CE", str_or_default(ci->params, id_REG_INPUTA_CE, "CE0"));
@ -1233,30 +1148,26 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} }
} }
tieoff_dsp_ports(ctx, cc, ci); tieoff_dsp_ports(ci);
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
}
} else if (ci->type == id_ALU54B) { void write_alu54(CellInfo *ci)
{
TileGroup tg; TileGroup tg;
Loc loc = ctx->getBelLocation(ci->bel); Loc loc = ctx->getBelLocation(ci->bel);
tg.tiles = get_dsp_tiles(ctx, ci->bel); tg.tiles = get_dsp_tiles(ci->bel);
std::string dsp = "ALU54_" + std::to_string(loc.z); std::string dsp = "ALU54_" + std::to_string(loc.z);
tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_INPUTC0_CLK", str_or_default(ci->params, id_REG_INPUTC0_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_INPUTC1_CLK", str_or_default(ci->params, id_REG_INPUTC1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK", tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CLK", str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
str_or_default(ci->params, id_REG_OPCODEOP0_0_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0")); tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_CE", str_or_default(ci->params, id_REG_OPCODEOP0_0_CE, "CE0"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST", tg.config.add_enum(dsp + ".REG_OPCODEOP0_0_RST", str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0"));
str_or_default(ci->params, id_REG_OPCODEOP0_0_RST, "RST0")); tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK", str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP1_0_CLK", tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK", str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
str_or_default(ci->params, id_REG_OPCODEOP1_0_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK", str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CLK",
str_or_default(ci->params, id_REG_OPCODEOP0_1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP1_1_CLK",
str_or_default(ci->params, id_REG_OPCODEOP1_1_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0")); tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_CE", str_or_default(ci->params, id_REG_OPCODEOP0_1_CE, "CE0"));
tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST", tg.config.add_enum(dsp + ".REG_OPCODEOP0_1_RST", str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
str_or_default(ci->params, id_REG_OPCODEOP0_1_RST, "RST0"));
tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CLK", str_or_default(ci->params, id_REG_OPCODEIN_0_CLK, "NONE"));
tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0")); tg.config.add_enum(dsp + ".REG_OPCODEIN_0_CE", str_or_default(ci->params, id_REG_OPCODEIN_0_CE, "CE0"));
tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0")); tg.config.add_enum(dsp + ".REG_OPCODEIN_0_RST", str_or_default(ci->params, id_REG_OPCODEIN_0_RST, "RST0"));
@ -1268,21 +1179,18 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE")); tg.config.add_enum(dsp + ".REG_FLAG_CLK", str_or_default(ci->params, id_REG_FLAG_CLK, "NONE"));
tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC")); tg.config.add_enum(dsp + ".MCPAT_SOURCE", str_or_default(ci->params, id_MCPAT_SOURCE, "STATIC"));
tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC")); tg.config.add_enum(dsp + ".MASKPAT_SOURCE", str_or_default(ci->params, id_MASKPAT_SOURCE, "STATIC"));
tg.config.add_word( tg.config.add_word(dsp + ".MASK01", parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"),
dsp + ".MASK01", 56, ci->name.c_str(ctx)));
parse_init_str(str_or_default(ci->params, id_MASK01, "0x00000000000000"), 56, ci->name.c_str(ctx)));
tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED")); tg.config.add_enum(dsp + ".CLK0_DIV", str_or_default(ci->params, id_CLK0_DIV, "ENABLED"));
tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED")); tg.config.add_enum(dsp + ".CLK1_DIV", str_or_default(ci->params, id_CLK1_DIV, "ENABLED"));
tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED")); tg.config.add_enum(dsp + ".CLK2_DIV", str_or_default(ci->params, id_CLK2_DIV, "ENABLED"));
tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED")); tg.config.add_enum(dsp + ".CLK3_DIV", str_or_default(ci->params, id_CLK3_DIV, "ENABLED"));
tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"), tg.config.add_word(dsp + ".MCPAT", parse_init_str(str_or_default(ci->params, id_MCPAT, "0x00000000000000"), 56,
56, ci->name.c_str(ctx)));
tg.config.add_word(dsp + ".MASKPAT",
parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"), 56,
ci->name.c_str(ctx))); ci->name.c_str(ctx)));
tg.config.add_word( tg.config.add_word(dsp + ".MASKPAT", parse_init_str(str_or_default(ci->params, id_MASKPAT, "0x00000000000000"),
dsp + ".RNDPAT", 56, ci->name.c_str(ctx)));
parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"), 56, ci->name.c_str(ctx))); tg.config.add_word(dsp + ".RNDPAT", parse_init_str(str_or_default(ci->params, id_RNDPAT, "0x00000000000000"),
56, ci->name.c_str(ctx)));
tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED")); tg.config.add_enum(dsp + ".GSR", str_or_default(ci->params, id_GSR, "ENABLED"));
tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC")); tg.config.add_enum(dsp + ".RESETMODE", str_or_default(ci->params, id_RESETMODE, "SYNC"));
tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT", tg.config.add_enum(dsp + ".FORCE_ZERO_BARREL_SHIFT",
@ -1309,11 +1217,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON"); tg.config.add_enum("MULT18_0.CIBOUT_BYP", "ON");
} }
} }
tieoff_dsp_ports(ctx, cc, ci); tieoff_dsp_ports(ci);
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
} else if (ci->type == id_EHXPLLL) { }
void write_pll(CellInfo *ci)
{
TileGroup tg; TileGroup tg;
tg.tiles = get_pll_tiles(ctx, ci->bel); tg.tiles = get_pll_tiles(ci->bel);
tg.config.add_enum("MODE", "EHXPLLL"); tg.config.add_enum("MODE", "EHXPLLL");
@ -1343,14 +1254,14 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0")); tg.config.add_enum("CLKOS_TRIM_DELAY", intstr_or_default(ci->params, id_CLKOS_TRIM_DELAY, "0"));
tg.config.add_enum("OUTDIVIDER_MUXA", str_or_default(ci->params, id_OUTDIVIDER_MUXA, tg.config.add_enum("OUTDIVIDER_MUXA",
ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK")); str_or_default(ci->params, id_OUTDIVIDER_MUXA, ci->getPort(id_CLKOP) ? "DIVA" : "REFCLK"));
tg.config.add_enum("OUTDIVIDER_MUXB", str_or_default(ci->params, id_OUTDIVIDER_MUXB, tg.config.add_enum("OUTDIVIDER_MUXB",
ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK")); str_or_default(ci->params, id_OUTDIVIDER_MUXB, ci->getPort(id_CLKOP) ? "DIVB" : "REFCLK"));
tg.config.add_enum("OUTDIVIDER_MUXC", str_or_default(ci->params, id_OUTDIVIDER_MUXC, tg.config.add_enum("OUTDIVIDER_MUXC",
ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK")); str_or_default(ci->params, id_OUTDIVIDER_MUXC, ci->getPort(id_CLKOP) ? "DIVC" : "REFCLK"));
tg.config.add_enum("OUTDIVIDER_MUXD", str_or_default(ci->params, id_OUTDIVIDER_MUXD, tg.config.add_enum("OUTDIVIDER_MUXD",
ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK")); str_or_default(ci->params, id_OUTDIVIDER_MUXD, ci->getPort(id_CLKOP) ? "DIVD" : "REFCLK"));
tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3)); tg.config.add_word("PLL_LOCK_MODE", int_to_bitvector(int_or_default(ci->params, id_PLL_LOCK_MODE, 0), 3));
@ -1389,10 +1300,13 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1)); int_to_bitvector(int_or_default(ci->attrs, id_MFG_ENABLE_FILTEROPAMP, 0), 1));
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
} else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) { }
void write_iol(CellInfo *ci)
{
Loc pio_loc = ctx->getBelLocation(ci->bel); Loc pio_loc = ctx->getBelLocation(ci->bel);
pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4; pio_loc.z -= ci->type == id_SIOLOGIC ? 2 : 4;
std::string pic_tile = get_pic_tile(ctx, ctx->getBelByLocation(pio_loc)); std::string pic_tile = get_pic_tile(ctx->getBelByLocation(pio_loc));
std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z]; std::string prim = std::string("IOLOGIC") + "ABCD"[pio_loc.z];
for (auto &param : ci->params) { for (auto &param : ci->params) {
if (param.first == ctx->id("DELAY.DEL_VALUE")) if (param.first == ctx->id("DELAY.DEL_VALUE"))
@ -1404,61 +1318,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
if (ci->getPort(id_LOADN) != nullptr) { if (ci->getPort(id_LOADN) != nullptr) {
cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN"); cc.tiles[pic_tile].add_enum(prim + ".LOADNMUX", "LOADN");
} }
} else if (ci->type == id_DCUA) { }
void write_dcu(CellInfo *ci)
{
TileGroup tg; TileGroup tg;
tg.tiles = get_dcu_tiles(ctx, ci->bel); tg.tiles = get_dcu_tiles(ci->bel);
tg.config.add_enum("DCU.MODE", "DCUA"); tg.config.add_enum("DCU.MODE", "DCUA");
#include "dcu_bitstream.h" #include "dcu_bitstream.h"
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
tieoff_dcu_ports(ctx, cc, ci); tieoff_dcu_ports(ci);
} else if (ci->type == id_EXTREFB) { }
TileGroup tg;
tg.tiles = get_dcu_tiles(ctx, ci->bel); void write_dqsbuf(CellInfo *ci)
tg.config.add_word("EXTREF.REFCK_DCBIAS_EN", {
parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_RTERM",
parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_PWDNB",
parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
cc.tilegroups.push_back(tg);
} else if (ci->type == id_PCSCLKDIV) {
Loc loc = ctx->getBelLocation(ci->bel);
std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
str_or_default(ci->params, id_GSR, "ENABLED"));
} else if (ci->type == id_DTR) {
cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
} else if (ci->type == id_OSCG) {
int div = int_or_default(ci->params, id_DIV, 128);
if (div == 128)
div = 127;
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div));
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
} else if (ci->type == id_USRMCLK) {
if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
} else if (ci->type == id_GSR) {
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("GSR.GSRMODE",
str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
} else if (ci->type == id_JTAGG) {
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
str_or_default(ci->params, id_ER1, "ENABLED"));
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
str_or_default(ci->params, id_ER2, "ENABLED"));
} else if (ci->type == id_CLKDIVF) {
Loc loc = ctx->getBelLocation(ci->bel);
bool r = loc.x > 5;
std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
} else if (ci->type == id_TRELLIS_ECLKBUF) {
} else if (ci->type == id_DQSBUFM) {
Loc loc = ctx->getBelLocation(ci->bel); Loc loc = ctx->getBelLocation(ci->bel);
bool l = loc.x < 10; bool l = loc.x < 10;
std::string pic = l ? "PICL" : "PICR"; std::string pic = l ? "PICL" : "PICR";
@ -1486,6 +1359,179 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
tg.config.add_enum("DQS.DDRDEL", ci->getPort(id_DDRDEL) != nullptr ? "DDRDEL" : "0"); tg.config.add_enum("DQS.DDRDEL", ci->getPort(id_DDRDEL) != nullptr ? "DDRDEL" : "0");
tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED")); tg.config.add_enum("DQS.GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
cc.tilegroups.push_back(tg); cc.tilegroups.push_back(tg);
}
void run(const std::string &base_config_file)
{
if (!base_config_file.empty()) {
std::ifstream config_file(base_config_file);
if (!config_file) {
log_error("failed to open base config file '%s'\n", base_config_file.c_str());
}
config_file >> cc;
} else {
switch (ctx->args.type) {
case ArchArgs::LFE5U_12F:
BaseConfigs::config_empty_lfe5u_25f(cc);
cc.chip_name = "LFE5U-12F";
break;
case ArchArgs::LFE5U_25F:
BaseConfigs::config_empty_lfe5u_25f(cc);
break;
case ArchArgs::LFE5U_45F:
BaseConfigs::config_empty_lfe5u_45f(cc);
break;
case ArchArgs::LFE5U_85F:
BaseConfigs::config_empty_lfe5u_85f(cc);
break;
case ArchArgs::LFE5UM_25F:
BaseConfigs::config_empty_lfe5um_25f(cc);
break;
case ArchArgs::LFE5UM_45F:
BaseConfigs::config_empty_lfe5um_45f(cc);
break;
case ArchArgs::LFE5UM_85F:
BaseConfigs::config_empty_lfe5um_85f(cc);
break;
case ArchArgs::LFE5UM5G_25F:
BaseConfigs::config_empty_lfe5um5g_25f(cc);
break;
case ArchArgs::LFE5UM5G_45F:
BaseConfigs::config_empty_lfe5um5g_45f(cc);
break;
case ArchArgs::LFE5UM5G_85F:
BaseConfigs::config_empty_lfe5um5g_85f(cc);
break;
default:
NPNR_ASSERT_FALSE("Unsupported device type");
}
}
cc.metadata.push_back("Part: " + ctx->get_full_chip_name());
// Clear out DCU tieoffs in base config if DCU used
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->type == id_DCUA) {
Loc loc = ctx->getBelLocation(ci->bel);
for (int i = 0; i < 12; i++) {
auto tiles = ctx->get_tiles_at_loc(loc.y - 1, loc.x + i);
for (const auto &tile : tiles) {
auto cc_tile = cc.tiles.find(tile.first);
if (cc_tile != cc.tiles.end()) {
cc_tile->second.cenums.clear();
cc_tile->second.cunknowns.clear();
}
}
}
}
}
// Add all set, configurable pips to the config
for (auto pip : ctx->getPips()) {
if (ctx->getBoundPipNet(pip) != nullptr) {
if (ctx->get_pip_class(pip) == 0) { // ignore fixed pips
std::string source = get_trellis_wirename(pip.location, ctx->getPipSrcWire(pip));
if (source.find("CLKI_PLL") != std::string::npos) {
// Special case - must set pip in all relevant tiles
for (auto equiv_pip : ctx->getPipsUphill(ctx->getPipDstWire(pip))) {
if (ctx->getPipSrcWire(equiv_pip) == ctx->getPipSrcWire(pip))
set_pip(equiv_pip);
}
} else {
set_pip(pip);
}
}
}
}
init_io_banks();
// Configure cells
for (auto &cell : ctx->cells) {
CellInfo *ci = cell.second.get();
if (ci->bel == BelId()) {
log_warning("found unplaced cell '%s' during bitstream gen\n", ci->name.c_str(ctx));
}
BelId bel = ci->bel;
if (ci->type == id_TRELLIS_COMB) {
write_comb(ci);
} else if (ci->type == id_TRELLIS_FF) {
write_ff(ci);
} else if (ci->type == id_TRELLIS_RAMW) {
std::string tname = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, "PLC2");
cc.tiles[tname].add_enum("SLICEC.MODE", "RAMW");
cc.tiles[tname].add_word("SLICEC.K0.INIT", std::vector<bool>(16, false));
cc.tiles[tname].add_word("SLICEC.K1.INIT", std::vector<bool>(16, false));
} else if (ci->type == id_TRELLIS_IO) {
write_io(ci);
} else if (ci->type == id_DCCA) {
write_dcc(ci);
} else if (ci->type == id_DCSC) {
std::set<std::string> dcs_tiles{"EBR_CMUX_LL", "EBR_CMUX_UL", "EBR_CMUX_LL_25K", "DSP_CMUX_UL"};
std::string tile = ctx->get_tile_by_type_loc(bel.location.y, bel.location.x, dcs_tiles);
std::string dcs = ctx->loc_info(bel)->bel_data[bel.index].name.get();
cc.tiles[tile].add_enum(dcs + ".DCSMODE", str_or_default(ci->attrs, id_DCSMODE, "POS"));
} else if (ci->type == id_DP16KD) {
write_bram(ci);
} else if (ci->type == id_MULT18X18D) {
write_mult18(ci);
} else if (ci->type == id_ALU54B) {
write_alu54(ci);
} else if (ci->type == id_EHXPLLL) {
write_pll(ci);
} else if (ci->type.in(id_IOLOGIC, id_SIOLOGIC)) {
write_iol(ci);
} else if (ci->type == id_DCUA) {
write_dcu(ci);
} else if (ci->type == id_EXTREFB) {
TileGroup tg;
tg.tiles = get_dcu_tiles(ci->bel);
tg.config.add_word("EXTREF.REFCK_DCBIAS_EN",
parse_config_str(get_or_default(ci->params, id_REFCK_DCBIAS_EN, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_RTERM",
parse_config_str(get_or_default(ci->params, id_REFCK_RTERM, Property(0)), 1));
tg.config.add_word("EXTREF.REFCK_PWDNB",
parse_config_str(get_or_default(ci->params, id_REFCK_PWDNB, Property(0)), 1));
cc.tilegroups.push_back(tg);
} else if (ci->type == id_PCSCLKDIV) {
Loc loc = ctx->getBelLocation(ci->bel);
std::string tname = ctx->get_tile_by_type_loc(loc.y + 1, loc.x, "BMID_0H");
cc.tiles[tname].add_enum("PCSCLKDIV" + std::to_string(loc.z),
str_or_default(ci->params, id_GSR, "ENABLED"));
} else if (ci->type == id_DTR) {
cc.tiles[ctx->get_tile_by_type("DTR")].add_enum("DTR.MODE", "DTR");
} else if (ci->type == id_OSCG) {
int div = int_or_default(ci->params, id_DIV, 128);
if (div == 128)
div = 127;
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("OSC.DIV", std::to_string(div));
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.DIV", std::to_string(div));
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("OSC.MODE", "OSCG");
cc.tiles[ctx->get_tile_by_type("EFB1_PICB1")].add_enum("CCLK.MODE", "_NONE_");
} else if (ci->type == id_USRMCLK) {
if (str_or_default(ctx->settings, ctx->id("arch.sysconfig.MASTER_SPI_PORT"), "") == "ENABLE")
log_warning("USRMCLK will not function correctly when MASTER_SPI_PORT is set to ENABLE.\n");
cc.tiles[ctx->get_tile_by_type("EFB3_PICB1")].add_enum("CCLK.MODE", "USRMCLK");
} else if (ci->type == id_GSR) {
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum(
"GSR.GSRMODE", str_or_default(ci->params, id_MODE, "ACTIVE_LOW"));
cc.tiles[ctx->get_tile_by_type("VIQ_BUF")].add_enum("GSR.SYNCMODE",
str_or_default(ci->params, id_SYNCMODE, "ASYNC"));
} else if (ci->type == id_JTAGG) {
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER1",
str_or_default(ci->params, id_ER1, "ENABLED"));
cc.tiles[ctx->get_tile_by_type("EFB0_PICB0")].add_enum("JTAG.ER2",
str_or_default(ci->params, id_ER2, "ENABLED"));
} else if (ci->type == id_CLKDIVF) {
Loc loc = ctx->getBelLocation(ci->bel);
bool r = loc.x > 5;
std::string clkdiv = std::string("CLKDIV_") + (r ? "R" : "L") + std::to_string(loc.z);
std::string tile = ctx->get_tile_by_type(std::string("ECLK_") + (r ? "R" : "L"));
cc.tiles[tile].add_enum(clkdiv + ".DIV", str_or_default(ci->params, id_DIV, "2.0"));
cc.tiles[tile].add_enum(clkdiv + ".GSR", str_or_default(ci->params, id_GSR, "DISABLED"));
} else if (ci->type == id_TRELLIS_ECLKBUF) {
} else if (ci->type == id_DQSBUFM) {
write_dqsbuf(ci);
} else if (ci->type == id_ECLKSYNCB) { } else if (ci->type == id_ECLKSYNCB) {
Loc loc = ctx->getBelLocation(ci->bel); Loc loc = ctx->getBelLocation(ci->bel);
bool r = loc.x > 5; bool r = loc.x > 5;
@ -1541,11 +1587,20 @@ void write_bitstream(Context *ctx, std::string base_config_file, std::string tex
} }
// Fixup tile names // Fixup tile names
fix_tile_names(ctx, cc); fix_tile_names();
}
};
} // namespace
void write_bitstream(Context *ctx, std::string base_config_file, std::string text_config_file)
{
ECP5Bitgen bitgen(ctx);
bitgen.run(base_config_file);
// Configure chip // Configure chip
if (!text_config_file.empty()) { if (!text_config_file.empty()) {
std::ofstream out_config(text_config_file); std::ofstream out_config(text_config_file);
out_config << cc; out_config << bitgen.cc;
} }
} }