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ice40: Creating packer tests

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Signed-off-by: David Shah <davey1576@gmail.com>
This commit is contained in:
David Shah 2018-06-12 14:19:26 +02:00
parent 47eeda40bc
commit 9ee6a6e114
4 changed files with 233 additions and 0 deletions
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39
ice40/pack_tests/ffmodes.v Normal file
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module top(input clk, cen, rst, ina, inb, output reg outa, outb, outc, outd);
reg temp0 = 1'b0, temp1 = 1'b0;
always @(posedge clk)
if (cen)
if(rst)
temp0 <= 1'b0;
else
temp0 <= ina;
always @(negedge clk)
if (ina)
if(rst)
temp1 <= 1'b1;
else
temp1 <= inb;
always @(posedge clk or negedge rst)
if(!rst)
outa <= 1'b0;
else
outa <= temp0;
always @(posedge clk)
outb <= temp1;
always @(negedge clk)
outc <= temp0;
always @(negedge clk or posedge rst)
if (rst)
outd <= 1'b1;
else
outd <= temp1;
endmodule

169
ice40/pack_tests/io_wrapper.v Normal file
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module io_wrapper(input clk_pin, cen_pin, rst_pin, ina_pin, inb_pin,
output outa_pin, outb_pin, outc_pin, outd_pin);
wire clk, cen, rst, ina, inb, outa, outb, outc, outd;
(* BEL="0_14_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) clk_iob (
.PACKAGE_PIN(clk_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(clk),
.D_IN_1()
);
(* BEL="0_14_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) cen_iob (
.PACKAGE_PIN(cen_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(cen),
.D_IN_1()
);
(* BEL="0_13_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) rst_iob (
.PACKAGE_PIN(rst_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(rst),
.D_IN_1()
);
(* BEL="0_13_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) ina_iob (
.PACKAGE_PIN(ina_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(ina),
.D_IN_1()
);
(* BEL="0_12_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0000_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) inb_iob (
.PACKAGE_PIN(inb_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(),
.D_OUT_1(),
.D_IN_0(inb),
.D_IN_1()
);
(* BEL="0_12_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) outa_iob (
.PACKAGE_PIN(outa_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(outa),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="0_11_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) outb_iob (
.PACKAGE_PIN(outb_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(outb),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="0_11_io0" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) outc_iob (
.PACKAGE_PIN(outc_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(outc),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
(* BEL="0_10_io1" *)
SB_IO #(
.PIN_TYPE(6'b 0110_01),
.PULLUP(1'b0),
.NEG_TRIGGER(1'b0)
) outd_iob (
.PACKAGE_PIN(outa_pin),
.LATCH_INPUT_VALUE(),
.CLOCK_ENABLE(),
.INPUT_CLK(),
.OUTPUT_CLK(),
.OUTPUT_ENABLE(),
.D_OUT_0(outd),
.D_OUT_1(),
.D_IN_0(),
.D_IN_1()
);
top top_i(.clk(clk), .rst(rst), .cen(cen), .ina(ina), .inb(inb), .outa(outa), .outb(outb), .outc(outc), .outd(outd));
endmodule

10
ice40/pack_tests/test.pcf Normal file
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set_io clk 1
set_io cen 2
set_io rst 3
set_io ina 4
set_io inb 7
set_io outa 8
set_io outb 9
set_io outc 10
set_io outd 11

15
ice40/pack_tests/test.sh Executable file
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#!/usr/bin/env bash
set -ex
NAME=${1%.v}
yosys -p "synth_ice40 -nocarry -top io_wrapper; write_json ${NAME}.json" $1 io_wrapper.v
../../nextpnr-ice40 --json ${NAME}.json --pack --asc ${NAME}.asc
icebox_vlog -p test.pcf ${NAME}.asc > ${NAME}_out.v
yosys -p "rename top gate\
read_verilog $1\
rename top gold\
hierarchy\
proc\
clk2fflogic\
miter -equiv -flatten -ignore_gold_x -make_outputs -make_outcmp gold gate miter\
sat -dump_vcd equiv_${NAME}.vcd -verify-no-timeout -timeout 20 -seq 10 -prove trigger 0 -prove-skip 1 -show-inputs -show-outputs miter" ${NAME}_out.v