Modify predictDelay signature
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@ -111,7 +111,7 @@ delay_t Context::getNetinfoRouteDelay(NetInfo *net_info, int user_idx) const
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if (cursor == src_wire)
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return delay + getWireDelay(src_wire).maxDelay();
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return predictDelay(src_wire, dst_wire);
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return predictDelay(net_info, net_info->users[user_idx]);
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}
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static uint32_t xorshift32(uint32_t x)
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@ -37,7 +37,6 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
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return 0;
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driver_gb = ctx->getBelGlobalBuf(driver_cell->bel);
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driver_loc = ctx->getBelLocation(driver_cell->bel);
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WireId drv_wire = ctx->getBelPinWire(driver_cell->bel, ctx->portPinFromId(net->driver.port));
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if (driver_gb)
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return 0;
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delay_t worst_slack = std::numeric_limits<delay_t>::max();
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@ -49,9 +48,8 @@ wirelen_t get_net_metric(const Context *ctx, const NetInfo *net, MetricType type
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if (load_cell->bel == BelId())
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continue;
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if (ctx->timing_driven && type == MetricType::COST) {
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WireId user_wire = ctx->getBelPinWire(load_cell->bel, ctx->portPinFromId(load.port));
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delay_t raw_wl = ctx->estimateDelay(drv_wire, user_wire);
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auto slack = load.budget - raw_wl;
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delay_t net_delay = ctx->predictDelay(net, load);
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auto slack = load.budget - net_delay;
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if (slack < 0)
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tns += slack;
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worst_slack = std::min(slack, worst_slack);
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@ -413,9 +413,13 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
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}
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delay_t Arch::predictDelay(WireId src, WireId dst) const
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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{
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return 200 * (abs(src.location.x - dst.location.x) + abs(src.location.y - dst.location.y));
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const auto& driver = net_info->driver;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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return 200 * (abs(driver_loc.x - sink_loc.x) + abs(driver_loc.y - sink_loc.y));
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}
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delay_t Arch::getBudgetOverride(NetInfo *net_info, int user_idx, delay_t budget) const { return budget; }
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@ -776,7 +776,7 @@ struct Arch : BaseCtx
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 20; }
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delay_t getRipupDelayPenalty() const { return 200; }
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float getDelayNS(delay_t v) const { return v * 0.001; }
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@ -403,12 +403,14 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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return (dx + dy) * grid_distance_to_delay;
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}
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delay_t Arch::predictDelay(WireId src, WireId dst) const
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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{
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const WireInfo &s = wires.at(src);
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const WireInfo &d = wires.at(dst);
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int dx = abs(s.x - d.x);
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int dy = abs(s.y - d.y);
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const auto& driver = net_info->driver;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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int dx = abs(driver_loc.x - driver_loc.x);
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int dy = abs(sink_loc.y - sink_locy);
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return (dx + dy) * grid_distance_to_delay;
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}
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@ -194,7 +194,7 @@ struct Arch : BaseCtx
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const std::vector<GroupId> &getGroupGroups(GroupId group) const;
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 0.01; }
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delay_t getRipupDelayPenalty() const { return 1.0; }
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float getDelayNS(delay_t v) const { return v; }
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@ -587,40 +587,23 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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return xscale * abs(xd) + yscale * abs(yd) + offset;
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}
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delay_t Arch::predictDelay(WireId src, WireId dst) const
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delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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{
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NPNR_ASSERT(src != WireId());
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int x1 = chip_info->wire_data[src.index].x;
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int y1 = chip_info->wire_data[src.index].y;
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const auto& driver = net_info->driver;
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auto driver_loc = getBelLocation(driver.cell->bel);
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auto sink_loc = getBelLocation(sink.cell->bel);
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NPNR_ASSERT(dst != WireId());
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int x2 = chip_info->wire_data[dst.index].x;
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int y2 = chip_info->wire_data[dst.index].y;
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if (driver.port == id_cout) {
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if (driver_loc.y == sink_loc.y)
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return 0;
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return 250;
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}
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int xd = x2 - x1, yd = y2 - y1;
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int xd = sink_loc.x - driver_loc.x, yd = sink_loc.y - driver_loc.y;
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int xscale = 120, yscale = 120, offset = 0;
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// if (chip_info->wire_data[src.index].type == WIRE_TYPE_SP4_VERT) {
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// yd = yd < -4 ? yd + 4 : (yd < 0 ? 0 : yd);
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// offset = 500;
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// }
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// Estimate for output mux
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for (const auto &bp : getWireBelPins(src)) {
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if (bp.pin == PIN_O && getBelType(bp.bel) == TYPE_ICESTORM_LC) {
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offset += 330;
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break;
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}
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}
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// Estimate for input mux
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for (const auto &bp : getWireBelPins(dst)) {
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if ((bp.pin == PIN_I0 || bp.pin == PIN_I1 || bp.pin == PIN_I2 || bp.pin == PIN_I3) &&
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getBelType(bp.bel) == TYPE_ICESTORM_LC) {
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offset += 260;
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break;
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}
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}
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if (driver.port == id_o) offset += 330;
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if (sink.port == id_i0 || sink.port == id_i1 || sink.port == id_i2 || sink.port == id_i3) offset += 260;
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return xscale * abs(xd) + yscale * abs(yd) + offset;
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}
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@ -697,7 +697,7 @@ struct Arch : BaseCtx
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// -------------------------------------------------
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delay_t estimateDelay(WireId src, WireId dst) const;
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delay_t predictDelay(WireId src, WireId dst) const;
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delay_t predictDelay(const NetInfo *net_info, const PortRef &sink) const;
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delay_t getDelayEpsilon() const { return 20; }
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delay_t getRipupDelayPenalty() const { return 200; }
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float getDelayNS(delay_t v) const { return v * 0.001; }
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