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Remove HACK for BUFG routing

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This commit is contained in:
Eddie Hung 2018-12-26 18:15:01 -08:00
parent a630758ca7
commit a0a6281d0d
1 changed files with 0 additions and 20 deletions
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20
common/router1.cc
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@ -445,26 +445,6 @@ struct Router1
auto dst_wire = ctx->getNetinfoSinkWire(net_info, net_info->users[user_idx]);
ripup_flag = false;
#ifdef ARCH_XC7
// Work around the fact that BUFG inputs have a logical location far away from its IMUX by introducing an "imux_wire" to guide A* routing
auto imux_wire = dst_wire;
const auto &dst_tw = torc_info->wire_to_tilewire[dst_wire.index];
const auto &tileInfo = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
const auto tileTypeName = torc_info->tiles.getTileTypeName(tileInfo.getTypeIndex());
if (boost::starts_with(tileTypeName, "CLK")) {
TilewireVector sources;
const_cast<DDB &>(*torc_info->ddb).expandTilewireSources(dst_tw, sources, false /*inUseTied*/, true /*inUseRegular*/, false /*inUseIrregular*/, false /*inUseRoutethrough*/);
std::cout << ctx->getWireName(torc_info->tilewire_to_wire(dst_tw)).str(ctx);
if (sources.size() == 1) {
imux_wire = torc_info->tilewire_to_wire(sources.front());
std::cout << " -> " << ctx->getWireName(imux_wire).str(ctx) << std::endl;
}
else
std::cout << " has " << sources.size() << " sources" << std::endl;
}
#endif
if (ctx->debug) {
log("Routing arc %d on net %s (%d arcs total):\n", user_idx, ctx->nameOf(net_info),
int(net_info->users.size()));