diff --git a/xc7/arch.cc b/xc7/arch.cc index 04464501..b0be78eb 100644 --- a/xc7/arch.cc +++ b/xc7/arch.cc @@ -37,8 +37,8 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string : ddb(new DDB(inDeviceName, inPackageName)), sites(ddb->getSites()), tiles(ddb->getTiles()), segments(ddb->getSegments()) { - bel_to_site_index.reserve(sites.getSiteCount()*4); - bel_to_loc.reserve(sites.getSiteCount()*4); + bel_to_site_index.reserve(sites.getSiteCount() * 4); + bel_to_loc.reserve(sites.getSiteCount() * 4); site_index_to_bel.resize(sites.getSiteCount()); site_index_to_type.resize(sites.getSiteCount()); BelId b; @@ -48,7 +48,8 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string const auto &pd = site.getPrimitiveDefPtr(); const auto &type = pd->getName(); const auto &tile_info = tiles.getTileInfo(site.getTileIndex()); - const auto x = (tile_info.getCol() + 1) / 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs + const auto x = (tile_info.getCol() + 1) / + 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs const auto y = tile_info.getRow(); if (type == "SLICEL" || type == "SLICEM") { bel_to_site_index.push_back(i); @@ -101,7 +102,7 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string const boost::regex bufg_o("(CMT|CLK)_BUFG_BUFGCTRL\\d+_O"); const boost::regex int_clk("CLK(_L)?[01]"); const boost::regex gclk("GCLK_(L_)?B\\d+(_EAST|_WEST)?"); - std::unordered_map> delay_lookup; + std::unordered_map> delay_lookup; Tilewire currentTilewire; boost::cmatch what; WireId w; @@ -130,15 +131,24 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string auto wireCount = tiles.getWireCount(tileTypeIndex); std::vector tile_delays(wireCount); for (WireIndex wireIndex(0); wireIndex < wireCount; wireIndex++) { - const WireInfo& wireInfo = tiles.getWireInfo(tileTypeIndex, wireIndex); + const WireInfo &wireInfo = tiles.getWireInfo(tileTypeIndex, wireIndex); auto wire_name = wireInfo.getName(); if (boost::regex_match(wire_name, what, re_124)) { switch (what.str(2)[0]) { - case '1': tile_delays[wireIndex] = 150; break; - case '2': tile_delays[wireIndex] = 170; break; - case '4': tile_delays[wireIndex] = 210; break; - case '6': tile_delays[wireIndex] = 210; break; - default: throw; + case '1': + tile_delays[wireIndex] = 150; + break; + case '2': + tile_delays[wireIndex] = 170; + break; + case '4': + tile_delays[wireIndex] = 210; + break; + case '6': + tile_delays[wireIndex] = 210; + break; + default: + throw; } } else if (boost::regex_match(wire_name, what, re_L)) { std::string l(what[2]); @@ -157,13 +167,26 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string tile_delays[wireIndex] = 190; } else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) { switch (what.str(2)[0]) { - case '1': tile_delays[wireIndex] = 280; break; - case '2': tile_delays[wireIndex] = 280; break; - case '3': tile_delays[wireIndex] = 180; break; - case '4': tile_delays[wireIndex] = 180; break; - case '5': tile_delays[wireIndex] = 80; break; - case '6': tile_delays[wireIndex] = 40; break; - default: throw; + case '1': + tile_delays[wireIndex] = 280; + break; + case '2': + tile_delays[wireIndex] = 280; + break; + case '3': + tile_delays[wireIndex] = 180; + break; + case '4': + tile_delays[wireIndex] = 180; + break; + case '5': + tile_delays[wireIndex] = 80; + break; + case '6': + tile_delays[wireIndex] = 40; + break; + default: + throw; } } } @@ -181,7 +204,7 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string num_wires = wire_to_tilewire.size(); wire_to_pips_downhill.resize(num_wires); - //std::unordered_map arc_to_pip; + // std::unordered_map arc_to_pip; ArcVector arcs; ExtendedWireInfo ewi(*ddb); PipId p; @@ -198,9 +221,9 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now) arcs.clear(); - const_cast(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, false /* inUseTied */, - true /*inUseRegular */, true /* inUseIrregular */, - !clb /* inUseRoutethrough */); + const_cast(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, + false /* inUseTied */, true /*inUseRegular */, + true /* inUseIrregular */, !clb /* inUseRoutethrough */); auto &pips = wire_to_pips_downhill[w.index]; pips.reserve(arcs.size()); @@ -228,7 +251,7 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string } pips.push_back(p.index); pip_to_arc.emplace_back(a); - //arc_to_pip.emplace(a, p.index); + // arc_to_pip.emplace(a, p.index); const auto &tw = a.getSinkTilewire(); pip_to_dst_wire.emplace_back(tilewire_to_wire(tw)); ++p.index; @@ -237,7 +260,7 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string } pip_to_arc.shrink_to_fit(); num_pips = pip_to_arc.size(); - + pip_to_dst_wire.reserve(num_pips); for (const auto &arc : pip_to_arc) { const auto &tw = arc.getSinkTilewire(); @@ -411,8 +434,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const throw; } } - } - else if (bel_type == id_PS7) { + } else if (bel_type == id_PS7) { // e.g. Convert DDRARB[0] -> DDRARB0 boost::erase_all(pin_name, "["); boost::erase_all(pin_name, "]"); @@ -560,28 +582,25 @@ IdString Arch::getPipName(PipId pip) const pip_name << ewi_src.mTileName << "." << ewi_src.mWireName << ".->." << ewi_dst.mWireName; return id(pip_name.str()); -//#if 1 -// int x = chip_info->pip_data[pip.index].x; -// int y = chip_info->pip_data[pip.index].y; -// -// std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get(); -// std::replace(src_name.begin(), src_name.end(), '/', '.'); -// -// std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get(); -// std::replace(dst_name.begin(), dst_name.end(), '/', '.'); -// -// return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name); -//#else -// return id(chip_info->pip_data[pip.index].name.get()); -//#endif + //#if 1 + // int x = chip_info->pip_data[pip.index].x; + // int y = chip_info->pip_data[pip.index].y; + // + // std::string src_name = chip_info->wire_data[chip_info->pip_data[pip.index].src].name.get(); + // std::replace(src_name.begin(), src_name.end(), '/', '.'); + // + // std::string dst_name = chip_info->wire_data[chip_info->pip_data[pip.index].dst].name.get(); + // std::replace(dst_name.begin(), dst_name.end(), '/', '.'); + // + // return id("X" + std::to_string(x) + "/Y" + std::to_string(y) + "/" + src_name + ".->." + dst_name); + //#else + // return id(chip_info->pip_data[pip.index].name.get()); + //#endif } // ----------------------------------------------------------------------- -BelId Arch::getPackagePinBel(const std::string &pin) const -{ - return getBelByName(id(pin)); -} +BelId Arch::getPackagePinBel(const std::string &pin) const { return getBelByName(id(pin)); } std::string Arch::getBelPackagePin(BelId bel) const { @@ -732,10 +751,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } -bool Arch::route() -{ - return router1(getCtx(), Router1Cfg(getCtx())); -} +bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); } // ----------------------------------------------------------------------- @@ -974,8 +990,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in if (port == id_O) return TMG_COMB_OUTPUT; return TMG_COMB_INPUT; - } - else if (cell->type == id_PS7) { + } else if (cell->type == id_PS7) { // TODO return TMG_IGNORE; } diff --git a/xc7/arch.h b/xc7/arch.h index 1847607b..d14ab9df 100644 --- a/xc7/arch.h +++ b/xc7/arch.h @@ -324,7 +324,8 @@ struct TorcInfo private: void _construct(); static std::vector construct_bel_to_site_index(Arch *ctx, const Sites &sites); - static std::vector construct_site_index_to_bel(Arch *ctx, const Sites &sites, const std::vector &bel_to_site_index); + static std::vector construct_site_index_to_bel(Arch *ctx, const Sites &sites, + const std::vector &bel_to_site_index); static std::vector construct_site_index_to_type(Arch *ctx, const Sites &sites); static std::vector construct_bel_to_loc(const Sites &sites, const Tiles &tiles, const int num_bels, const std::vector &site_index_to_type); @@ -332,8 +333,8 @@ struct TorcInfo construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles, std::unordered_map &segment_to_wire, std::unordered_map &trivial_to_wire); - static std::vector construct_wire_to_delay(const Tiles &tiles, const std::vector &wire_to_tilewire, - const DDB &ddb); + static std::vector + construct_wire_to_delay(const Tiles &tiles, const std::vector &wire_to_tilewire, const DDB &ddb); static std::vector construct_pip_to_arc(const std::vector &wire_to_tilewire, const DDB &ddb, std::vector> &wire_to_pips_uphill, std::vector> &wire_to_pips_downhill); @@ -678,10 +679,7 @@ struct Arch : BaseCtx return wire_to_net[wire.index]; } - WireId getConflictingWireWire(WireId wire) const - { - return wire; - } + WireId getConflictingWireWire(WireId wire) const { return wire; } NetInfo *getConflictingWireNet(WireId wire) const { @@ -779,10 +777,7 @@ struct Arch : BaseCtx return pip_to_net[pip.index]; } - WireId getConflictingPipWire(PipId pip) const - { - return WireId(); - } + WireId getConflictingPipWire(PipId pip) const { return WireId(); } NetInfo *getConflictingPipNet(PipId pip) const { @@ -859,10 +854,10 @@ struct Arch : BaseCtx PipRange getPipsUphill(WireId wire) const { PipRange range; - //NPNR_ASSERT(wire != WireId()); - //const auto &pips = torc_info->wire_to_pips_uphill[wire.index]; - //range.b.cursor = pips.data(); - //range.e.cursor = range.b.cursor + pips.size(); + // NPNR_ASSERT(wire != WireId()); + // const auto &pips = torc_info->wire_to_pips_uphill[wire.index]; + // range.b.cursor = pips.data(); + // range.e.cursor = range.b.cursor + pips.size(); return range; } diff --git a/xc7/delay.cc b/xc7/delay.cc index 3bef3dfc..0df02f7e 100644 --- a/xc7/delay.cc +++ b/xc7/delay.cc @@ -104,7 +104,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex()); const auto &dst_tw = torc_info->wire_to_tilewire[dst.index]; const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex()); - auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1)/ 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs + auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1) / + 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow()); #if 1 auto div_LH = std::div(abs_delta_x, 12); @@ -118,10 +119,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const auto div_V2 = std::div(div_V4.rem, 2); auto num_H1 = div_H2.rem; auto num_V1 = div_V2.rem; - return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 - + (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 - + (div_H2.quot + div_V2.quot) * 170 - + (num_H1 + num_V1) * 150; + return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 + + (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 + + (num_H1 + num_V1) * 150; #else return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y); #endif @@ -146,10 +146,9 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const auto div_V2 = std::div(div_V4.rem, 2); auto num_H1 = div_H2.rem; auto num_V1 = div_V2.rem; - return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 - + (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 - + (div_H2.quot + div_V2.quot) * 170 - + (num_H1 + num_V1) * 150; + return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 + + (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 + + (num_H1 + num_V1) * 150; #else return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y); #endif diff --git a/xc7/xdl.cc b/xc7/xdl.cc index 97a18538..32546490 100644 --- a/xc7/xdl.cc +++ b/xc7/xdl.cc @@ -136,7 +136,7 @@ void write_xdl(const Context *ctx, std::ostream &out) NPNR_ASSERT(init.size() == (1u << lut_inputs.size())); unsigned n = 0; for (unsigned i = 0; i < init.size(); ++i) { - if (init[init.size()-1-i] == '0') + if (init[init.size() - 1 - i] == '0') continue; if (n++ > 0) value += "+";