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This commit is contained in:
Eddie Hung 2018-11-27 12:28:48 -08:00
parent ae9ccfa5ad
commit a0b6d3b19b
4 changed files with 83 additions and 74 deletions
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71
xc7/arch.cc
View File

@ -48,7 +48,8 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
const auto &pd = site.getPrimitiveDefPtr(); const auto &pd = site.getPrimitiveDefPtr();
const auto &type = pd->getName(); const auto &type = pd->getName();
const auto &tile_info = tiles.getTileInfo(site.getTileIndex()); const auto &tile_info = tiles.getTileInfo(site.getTileIndex());
const auto x = (tile_info.getCol() + 1) / 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs const auto x = (tile_info.getCol() + 1) /
2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
const auto y = tile_info.getRow(); const auto y = tile_info.getRow();
if (type == "SLICEL" || type == "SLICEM") { if (type == "SLICEL" || type == "SLICEM") {
bel_to_site_index.push_back(i); bel_to_site_index.push_back(i);
@ -134,11 +135,20 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
auto wire_name = wireInfo.getName(); auto wire_name = wireInfo.getName();
if (boost::regex_match(wire_name, what, re_124)) { if (boost::regex_match(wire_name, what, re_124)) {
switch (what.str(2)[0]) { switch (what.str(2)[0]) {
case '1': tile_delays[wireIndex] = 150; break; case '1':
case '2': tile_delays[wireIndex] = 170; break; tile_delays[wireIndex] = 150;
case '4': tile_delays[wireIndex] = 210; break; break;
case '6': tile_delays[wireIndex] = 210; break; case '2':
default: throw; tile_delays[wireIndex] = 170;
break;
case '4':
tile_delays[wireIndex] = 210;
break;
case '6':
tile_delays[wireIndex] = 210;
break;
default:
throw;
} }
} else if (boost::regex_match(wire_name, what, re_L)) { } else if (boost::regex_match(wire_name, what, re_L)) {
std::string l(what[2]); std::string l(what[2]);
@ -157,13 +167,26 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
tile_delays[wireIndex] = 190; tile_delays[wireIndex] = 190;
} else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) { } else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) {
switch (what.str(2)[0]) { switch (what.str(2)[0]) {
case '1': tile_delays[wireIndex] = 280; break; case '1':
case '2': tile_delays[wireIndex] = 280; break; tile_delays[wireIndex] = 280;
case '3': tile_delays[wireIndex] = 180; break; break;
case '4': tile_delays[wireIndex] = 180; break; case '2':
case '5': tile_delays[wireIndex] = 80; break; tile_delays[wireIndex] = 280;
case '6': tile_delays[wireIndex] = 40; break; break;
default: throw; case '3':
tile_delays[wireIndex] = 180;
break;
case '4':
tile_delays[wireIndex] = 180;
break;
case '5':
tile_delays[wireIndex] = 80;
break;
case '6':
tile_delays[wireIndex] = 40;
break;
default:
throw;
} }
} }
} }
@ -198,9 +221,9 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now) tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now)
arcs.clear(); arcs.clear();
const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, false /* inUseTied */, const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone,
true /*inUseRegular */, true /* inUseIrregular */, false /* inUseTied */, true /*inUseRegular */,
!clb /* inUseRoutethrough */); true /* inUseIrregular */, !clb /* inUseRoutethrough */);
auto &pips = wire_to_pips_downhill[w.index]; auto &pips = wire_to_pips_downhill[w.index];
pips.reserve(arcs.size()); pips.reserve(arcs.size());
@ -411,8 +434,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
throw; throw;
} }
} }
} } else if (bel_type == id_PS7) {
else if (bel_type == id_PS7) {
// e.g. Convert DDRARB[0] -> DDRARB0 // e.g. Convert DDRARB[0] -> DDRARB0
boost::erase_all(pin_name, "["); boost::erase_all(pin_name, "[");
boost::erase_all(pin_name, "]"); boost::erase_all(pin_name, "]");
@ -578,10 +600,7 @@ IdString Arch::getPipName(PipId pip) const
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
BelId Arch::getPackagePinBel(const std::string &pin) const BelId Arch::getPackagePinBel(const std::string &pin) const { return getBelByName(id(pin)); }
{
return getBelByName(id(pin));
}
std::string Arch::getBelPackagePin(BelId bel) const std::string Arch::getBelPackagePin(BelId bel) const
{ {
@ -732,10 +751,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); } bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
bool Arch::route() bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
{
return router1(getCtx(), Router1Cfg(getCtx()));
}
// ----------------------------------------------------------------------- // -----------------------------------------------------------------------
@ -974,8 +990,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
if (port == id_O) if (port == id_O)
return TMG_COMB_OUTPUT; return TMG_COMB_OUTPUT;
return TMG_COMB_INPUT; return TMG_COMB_INPUT;
} } else if (cell->type == id_PS7) {
else if (cell->type == id_PS7) {
// TODO // TODO
return TMG_IGNORE; return TMG_IGNORE;
} }

17
xc7/arch.h
View File

@ -324,7 +324,8 @@ struct TorcInfo
private: private:
void _construct(); void _construct();
static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites); static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites);
static std::vector<BelId> construct_site_index_to_bel(Arch *ctx, const Sites &sites, const std::vector<SiteIndex> &bel_to_site_index); static std::vector<BelId> construct_site_index_to_bel(Arch *ctx, const Sites &sites,
const std::vector<SiteIndex> &bel_to_site_index);
static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites); static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
static std::vector<Loc> construct_bel_to_loc(const Sites &sites, const Tiles &tiles, const int num_bels, static std::vector<Loc> construct_bel_to_loc(const Sites &sites, const Tiles &tiles, const int num_bels,
const std::vector<IdString> &site_index_to_type); const std::vector<IdString> &site_index_to_type);
@ -332,8 +333,8 @@ struct TorcInfo
construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles, construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles,
std::unordered_map<Segments::SegmentReference, int> &segment_to_wire, std::unordered_map<Segments::SegmentReference, int> &segment_to_wire,
std::unordered_map<Tilewire, int> &trivial_to_wire); std::unordered_map<Tilewire, int> &trivial_to_wire);
static std::vector<DelayInfo> construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire, static std::vector<DelayInfo>
const DDB &ddb); construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb);
static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb, static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb,
std::vector<std::vector<int>> &wire_to_pips_uphill, std::vector<std::vector<int>> &wire_to_pips_uphill,
std::vector<std::vector<int>> &wire_to_pips_downhill); std::vector<std::vector<int>> &wire_to_pips_downhill);
@ -678,10 +679,7 @@ struct Arch : BaseCtx
return wire_to_net[wire.index]; return wire_to_net[wire.index];
} }
WireId getConflictingWireWire(WireId wire) const WireId getConflictingWireWire(WireId wire) const { return wire; }
{
return wire;
}
NetInfo *getConflictingWireNet(WireId wire) const NetInfo *getConflictingWireNet(WireId wire) const
{ {
@ -779,10 +777,7 @@ struct Arch : BaseCtx
return pip_to_net[pip.index]; return pip_to_net[pip.index];
} }
WireId getConflictingPipWire(PipId pip) const WireId getConflictingPipWire(PipId pip) const { return WireId(); }
{
return WireId();
}
NetInfo *getConflictingPipNet(PipId pip) const NetInfo *getConflictingPipNet(PipId pip) const
{ {

17
xc7/delay.cc
View File

@ -104,7 +104,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex()); const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
const auto &dst_tw = torc_info->wire_to_tilewire[dst.index]; const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex()); const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1)/ 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1) /
2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow()); auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
#if 1 #if 1
auto div_LH = std::div(abs_delta_x, 12); auto div_LH = std::div(abs_delta_x, 12);
@ -118,10 +119,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
auto div_V2 = std::div(div_V4.rem, 2); auto div_V2 = std::div(div_V4.rem, 2);
auto num_H1 = div_H2.rem; auto num_H1 = div_H2.rem;
auto num_V1 = div_V2.rem; auto num_V1 = div_V2.rem;
return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
+ (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
+ (div_H2.quot + div_V2.quot) * 170 (num_H1 + num_V1) * 150;
+ (num_H1 + num_V1) * 150;
#else #else
return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y); return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
#endif #endif
@ -146,10 +146,9 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
auto div_V2 = std::div(div_V4.rem, 2); auto div_V2 = std::div(div_V4.rem, 2);
auto num_H1 = div_H2.rem; auto num_H1 = div_H2.rem;
auto num_V1 = div_V2.rem; auto num_V1 = div_V2.rem;
return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
+ (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
+ (div_H2.quot + div_V2.quot) * 170 (num_H1 + num_V1) * 150;
+ (num_H1 + num_V1) * 150;
#else #else
return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y); return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
#endif #endif