clangformat
This commit is contained in:
Eddie Hung
parent
ae9ccfa5ad
commit
a0b6d3b19b
71
xc7/arch.cc
71
xc7/arch.cc
@ -48,7 +48,8 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
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const auto &pd = site.getPrimitiveDefPtr();
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const auto &type = pd->getName();
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const auto &tile_info = tiles.getTileInfo(site.getTileIndex());
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const auto x = (tile_info.getCol() + 1) / 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
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const auto x = (tile_info.getCol() + 1) /
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2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
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const auto y = tile_info.getRow();
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if (type == "SLICEL" || type == "SLICEM") {
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bel_to_site_index.push_back(i);
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@ -134,11 +135,20 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
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auto wire_name = wireInfo.getName();
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if (boost::regex_match(wire_name, what, re_124)) {
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switch (what.str(2)[0]) {
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case '1': tile_delays[wireIndex] = 150; break;
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case '2': tile_delays[wireIndex] = 170; break;
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case '4': tile_delays[wireIndex] = 210; break;
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case '6': tile_delays[wireIndex] = 210; break;
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default: throw;
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case '1':
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tile_delays[wireIndex] = 150;
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break;
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case '2':
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tile_delays[wireIndex] = 170;
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break;
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case '4':
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tile_delays[wireIndex] = 210;
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break;
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case '6':
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tile_delays[wireIndex] = 210;
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break;
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default:
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throw;
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}
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} else if (boost::regex_match(wire_name, what, re_L)) {
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std::string l(what[2]);
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@ -157,13 +167,26 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
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tile_delays[wireIndex] = 190;
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} else if (boost::regex_match(wire_name, what, re_CLB_I1_6)) {
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switch (what.str(2)[0]) {
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case '1': tile_delays[wireIndex] = 280; break;
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case '2': tile_delays[wireIndex] = 280; break;
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case '3': tile_delays[wireIndex] = 180; break;
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case '4': tile_delays[wireIndex] = 180; break;
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case '5': tile_delays[wireIndex] = 80; break;
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case '6': tile_delays[wireIndex] = 40; break;
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default: throw;
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case '1':
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tile_delays[wireIndex] = 280;
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break;
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case '2':
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tile_delays[wireIndex] = 280;
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break;
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case '3':
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tile_delays[wireIndex] = 180;
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break;
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case '4':
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tile_delays[wireIndex] = 180;
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break;
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case '5':
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tile_delays[wireIndex] = 80;
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break;
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case '6':
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tile_delays[wireIndex] = 40;
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break;
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default:
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throw;
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}
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}
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}
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@ -198,9 +221,9 @@ TorcInfo::TorcInfo(Arch *ctx, const std::string &inDeviceName, const std::string
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tileTypeName, "CLB"); // Disable all CLB route-throughs (i.e. LUT in->out, LUT A->AMUX, for now)
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arcs.clear();
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const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone, false /* inUseTied */,
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true /*inUseRegular */, true /* inUseIrregular */,
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!clb /* inUseRoutethrough */);
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const_cast<DDB &>(*ddb).expandSegmentSinks(currentTilewire, arcs, DDB::eExpandDirectionNone,
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false /* inUseTied */, true /*inUseRegular */,
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true /* inUseIrregular */, !clb /* inUseRoutethrough */);
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auto &pips = wire_to_pips_downhill[w.index];
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pips.reserve(arcs.size());
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@ -411,8 +434,7 @@ WireId Arch::getBelPinWire(BelId bel, IdString pin) const
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throw;
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}
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}
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}
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else if (bel_type == id_PS7) {
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} else if (bel_type == id_PS7) {
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// e.g. Convert DDRARB[0] -> DDRARB0
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boost::erase_all(pin_name, "[");
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boost::erase_all(pin_name, "]");
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@ -578,10 +600,7 @@ IdString Arch::getPipName(PipId pip) const
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// -----------------------------------------------------------------------
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BelId Arch::getPackagePinBel(const std::string &pin) const
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{
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return getBelByName(id(pin));
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}
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BelId Arch::getPackagePinBel(const std::string &pin) const { return getBelByName(id(pin)); }
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std::string Arch::getBelPackagePin(BelId bel) const
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{
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@ -732,10 +751,7 @@ bool Arch::getBudgetOverride(const NetInfo *net_info, const PortRef &sink, delay
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bool Arch::place() { return placer1(getCtx(), Placer1Cfg(getCtx())); }
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bool Arch::route()
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{
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return router1(getCtx(), Router1Cfg(getCtx()));
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}
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bool Arch::route() { return router1(getCtx(), Router1Cfg(getCtx())); }
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// -----------------------------------------------------------------------
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@ -974,8 +990,7 @@ TimingPortClass Arch::getPortTimingClass(const CellInfo *cell, IdString port, in
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if (port == id_O)
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return TMG_COMB_OUTPUT;
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return TMG_COMB_INPUT;
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}
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else if (cell->type == id_PS7) {
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} else if (cell->type == id_PS7) {
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// TODO
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return TMG_IGNORE;
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}
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17
xc7/arch.h
17
xc7/arch.h
@ -324,7 +324,8 @@ struct TorcInfo
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private:
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void _construct();
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static std::vector<SiteIndex> construct_bel_to_site_index(Arch *ctx, const Sites &sites);
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static std::vector<BelId> construct_site_index_to_bel(Arch *ctx, const Sites &sites, const std::vector<SiteIndex> &bel_to_site_index);
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static std::vector<BelId> construct_site_index_to_bel(Arch *ctx, const Sites &sites,
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const std::vector<SiteIndex> &bel_to_site_index);
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static std::vector<IdString> construct_site_index_to_type(Arch *ctx, const Sites &sites);
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static std::vector<Loc> construct_bel_to_loc(const Sites &sites, const Tiles &tiles, const int num_bels,
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const std::vector<IdString> &site_index_to_type);
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@ -332,8 +333,8 @@ struct TorcInfo
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construct_wire_to_tilewire(const Segments &segments, const Tiles &tiles,
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std::unordered_map<Segments::SegmentReference, int> &segment_to_wire,
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std::unordered_map<Tilewire, int> &trivial_to_wire);
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static std::vector<DelayInfo> construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire,
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const DDB &ddb);
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static std::vector<DelayInfo>
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construct_wire_to_delay(const Tiles &tiles, const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb);
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static std::vector<Arc> construct_pip_to_arc(const std::vector<Tilewire> &wire_to_tilewire, const DDB &ddb,
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std::vector<std::vector<int>> &wire_to_pips_uphill,
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std::vector<std::vector<int>> &wire_to_pips_downhill);
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@ -678,10 +679,7 @@ struct Arch : BaseCtx
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return wire_to_net[wire.index];
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}
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WireId getConflictingWireWire(WireId wire) const
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{
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return wire;
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}
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WireId getConflictingWireWire(WireId wire) const { return wire; }
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NetInfo *getConflictingWireNet(WireId wire) const
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{
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@ -779,10 +777,7 @@ struct Arch : BaseCtx
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return pip_to_net[pip.index];
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}
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WireId getConflictingPipWire(PipId pip) const
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{
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return WireId();
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}
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WireId getConflictingPipWire(PipId pip) const { return WireId(); }
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NetInfo *getConflictingPipNet(PipId pip) const
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{
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17
xc7/delay.cc
17
xc7/delay.cc
@ -104,7 +104,8 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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const auto &src_info = torc_info->tiles.getTileInfo(src_tw.getTileIndex());
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const auto &dst_tw = torc_info->wire_to_tilewire[dst.index];
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const auto &dst_info = torc_info->tiles.getTileInfo(dst_tw.getTileIndex());
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auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1)/ 2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
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auto abs_delta_x = (abs(src_info.getCol() - dst_info.getCol()) + 1) /
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2; // Divide by 2 because XDL coordinate space counts the INT tiles between CLBs
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auto abs_delta_y = abs(src_info.getRow() - dst_info.getRow());
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#if 1
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auto div_LH = std::div(abs_delta_x, 12);
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@ -118,10 +119,9 @@ delay_t Arch::estimateDelay(WireId src, WireId dst) const
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auto div_V2 = std::div(div_V4.rem, 2);
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auto num_H1 = div_H2.rem;
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auto num_V1 = div_V2.rem;
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return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350
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+ (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210
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+ (div_H2.quot + div_V2.quot) * 170
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+ (num_H1 + num_V1) * 150;
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return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
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(div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
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(num_H1 + num_V1) * 150;
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#else
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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#endif
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@ -146,10 +146,9 @@ delay_t Arch::predictDelay(const NetInfo *net_info, const PortRef &sink) const
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auto div_V2 = std::div(div_V4.rem, 2);
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auto num_H1 = div_H2.rem;
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auto num_V1 = div_V2.rem;
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return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350
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+ (div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210
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+ (div_H2.quot + div_V2.quot) * 170
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+ (num_H1 + num_V1) * 150;
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return div_LH.quot * 360 + div_LVB.quot * 300 + div_LV.quot * 350 +
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(div_H6.quot + div_H4.quot + div_V6.quot + div_V4.quot) * 210 + (div_H2.quot + div_V2.quot) * 170 +
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(num_H1 + num_V1) * 150;
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#else
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return std::max(150, 33 * abs_delta_x + 66 * abs_delta_y);
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#endif
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